60 mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 36-37

  Takahashi, Masafumi ^a   Hamada, Mototsugu ^a   Nishikawa, Tsuyoshi ^a   Arakida, Hideho ^a   Tsuboi, Yoshiaki ^a   Fujita, Tetsuya ^a   Hatori, Fumihiro ^a   Mita, Shinji ^a   Suzuki, Kojirou ^a   Chiba, Akihiko ^a   Terazawa, Toshihiro ^a   Sano, Fumihiko ^a   Watanabe, Yoshinori ^a   Momose, Hiroshi ^a   Usami, Kimiyoshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; FLIP FLOP CIRCUITS; IMAGE CODING; INTEGRATED CIRCUIT LAYOUT; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; STANDARDS;

CLUSTERED VOLTAGE SCALING (CVS) TECHNIQUE; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS; STATIC RANDOM ACCESS MEMORY (SRAM);

VIDEO SIGNAL PROCESSING;

EID: 0031652001     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)