An SoC with two multimedia DSPs and a RISC core for video compression applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Stolberg, H J ^a   Moch, S ^a   Friebe, L ^a   Dehnhardt, A ^a   Kulaczewski, M B ^a   Berekovic, M ^a   Pirsch, P ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED SIMPLE PROFILE (ASP); QUARTER-PEL MOTION COMPENSATION (QMC); REGION OF INTEREST (ROI); STREAM PROCESSOR (SP);

ALGORITHMS; DATA PROCESSING; DATA STORAGE EQUIPMENT; MICROPROCESSOR CHIPS; MOTION COMPENSATION; OPTIMIZATION; REDUCED INSTRUCTION SET COMPUTING; SIGNAL PROCESSING; WAVE FILTERS;

IMAGE COMPRESSION;

EID: 84867695624     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. F. Pirsch et al., "VLSI Architectures for MPEG-4," Proc. Int. Symp. VLSI Technology, Systems, and Applications, April 2003.
2. J. Williams et al., "A 3.2 GOPS Multiprocessor DSP for Communication Applications," ISSCC Digest of Technical Papers, Feb. 2000.
3. Sigma Designs, "EM8470 Series: MPEG-4 Decoder for Set-Top, DVD, and Streaming Applications," Product Brief, 2002.