A survey of processors with explicit multithreading

ACM Computing Surveys

Volumn 35, Issue 1, 2003, Pages 29-63

  Ungerer, Theo ^a   Robič, Borut ^b   Šilc, Jurij ^c  

^a UNIVERSITY OF AUGSBURG   (Germany)

^b UNIVERSITY OF LJUBLJANA   (Slovenia)

^c JO EF STEFAN INSTITUTE   (Slovenia)

Author keywords

Blocked multithreading; Interleaved multithreading; Simultaneous multithreading

Indexed keywords

BLOCKED MULTITHREADING; INTERLEAVED MULTITHREADING; MULTIPROGRAMMING WORKLOADS; SIMULTANEOUS MULTITHREADING;

BANDWIDTH; COMPUTER HARDWARE; CONTROL SYSTEMS; MICROPROCESSOR CHIPS; MULTIPROGRAMMING; NETWORK PROTOCOLS; PROGRAM PROCESSORS;

MULTIPROCESSING SYSTEMS;

EID: 2042458649     PISSN: 03600300     EISSN: 03600300     Source Type: Journal    
DOI: 10.1145/641865.641867     Document Type: Review

References (110)

1. AGARWAL, A., BIANCHINI, R., CHAIKEN, D., JOHNSON, K. L., KRANZ, D., KUBIATOWICZ, J., LIM, B. H., MACKENZIE, K., AND YEUNG, D. 1995. The MIT Alewife machine: architecture and performance. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (Santa Margherita Ligure, Italy). 2-13.
2. AGARWAL, A., KUBIATOWICZ, J., KRANZ, D., LIM, B. H., YEOUNG, D., D'SOUZA, G., AND PARKIN, M. 1993. Sparcle: an evolutionary processor design for large-scale multiprocessors. IEEE Micro 13, 3, 48-61.
3. AKKARY, H. AND DRISCOLL, M. A. 1998. A dynamic multithreading processor. In Proceedings of the 31st Annual International Symposium on Microarchitecture (Dallas, TX). 226-236.
4. ALLEN, F., ALMASI, G., ANDREONI, W., BEECE, D., BERNE, B. J., BRIGHT, A., BRUNHEROTO, J., CASCAVAL, C., CASTANOS, J., COTEUS, P., CRUMLEY, P., CURIONI, A., DENNEAU, M., DONATH, W., ELEFTHERIOU, M., PITCH, B., FLEISCHER, B., GEORGIOU, C. J., GERMAIN, R., GIAMPAPA, M., GRESH, D., GUPTA, M., HARING, R., Ho, H., HOCHSCHILD, P., HUMMEL, S., JONAS, T., LIEBER, D., MARTYNA, G., MATURU, K., MOREIRA, J., NEWNS, D., NEWTON, M., PHILHOWER, R., PICUNKO, T., PITERA, J., PITMAN, M., RAND, R., ROYYURU, A., SALAPURA, V., SANOMIYA, A., SHAH, R., SHAM, Y., SINGH, S., SNIR, M., SUITS, R., SWETZ, R., SWOPE, W. C., VISHNUMURTHY, N., WARD, T. G. J., WARREN, H., AND ZHOU, R. 2001. Blue Gene: a vision for protein science using a petaflops supercomputer. IBM Syst. J. 40, 2, 310-326.
5. ALMASI, G. S. AND GOTTLIEB, A. 1994. Highly Parallel Computing, 2nd ed. Benjamin/Cummings, Menlo Park, CA.
6. ALVERSON, G., KAHAN, S., KORRY, R., MCCANN, C., AND SMITH, B. J. 1995. Scheduling on the Tera MTA. In Lecture Notes in Computer Science, vol. 949. Springer-Verlag, Heidelberg, Germany. 19-44.
7. ALVERSON, R., CALLAHAN, D., CUMMINGS, D., KOBLENZ, B., PORTERFIELD, A., AND SMITH, B. J. 1990. The Tera computer system. In Proceedings of the 4th International Conference on Supercomputing (Amsterdam, The Netherlands). 1-6.
8. BACH, P., BRAUN, M., FORMELLA, A., FRIEDRICH, J., GRÜN, T., AND LINCHTENAU, C. 1997. Building the 4 processor SB-PRAM prototype. In Proceedings of the 30th Hawaii International Conference on System Science (Maui, HI). 5:14-23.
9. BARROSO, L. A., GHARACHORLOO, K., MCNAMARA, R., NOWATZYK, A., QADEER, S., SANO, B., SMITH, S., STETS, R., AND VERGHESE, B. 2000. Piranha: a scalable architecture based on single-chip multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture (Vancouver, B.C., Canada). 282-293.
10. BOLYCHEVSKY, A., JESSHOPE, C. R., AND MUCHNIK, V. B. 1996. Dynamic scheduling in RISC architectures. IEE P. Comput. Dig. Itch. 143, 5, 309-317.
11. BOOTHE, R. F. 1993. Evaluation of multithreading and caching in large shared memory parallel computers. Tech. Rep. UCB/CSD-93-766. Computer Science Division, University of California, Berkeley, Berkeley, CA.
12. BOOTHE, R. F. AND RANADE, A. 1992. Improved multithreading techniques for hiding communication latency in multiprocessors. In Proceedings of the 19th International Symposium on Computer Architecture (Gold Coast, Australia). 214-223.
13. BORKENHAGEN, J. M., EICKEMEYER, R. J., KALLA, R. N., AND KUNKEL, S. R. 2000. A multithreaded PowerPC processor for commercial servers. IBM J. Res. Dev. 44, 6, 885-898.
14. BRINKSCHULTE, U., BECHINA, A., PICIOROAGA, F., SCHNEIDER, E., UNGERER, T., KREUZINGER, J., AND PFEFFER, M. 2000. A microkernel middleware architecture for distributed embedded real-time systems. In Proceedings of the 20th IEEE Symposium on Reliable Distributed Systems (New Orleans LA). 218-226.
15. BRINKSCHULTE, U., KRAKOWSKI, C., KREUZINGER, J., AND UNGERER, T. 1999a. A multithreaded Java microcontroller for thread-oriented real-time event-handling. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Newport Beach, CA). 34-39.
16. BRINKSCHULTE, U., KRAKOWSKI, C., MARSTON, R., KREUZINGER, J., AND UNGERER, T. 1999b. The Komodo project: thread-based event handling supported by a multithreaded Java microcontroller. In Proceedings of the 25th Euromicro Conference (Milan, Italy). 122-128.
17. BRINKSCHULTE, U., KREUZINGER, J., PFEFFER, M., AND UNGERER, T. 2002. A scheduling technique providing a strict isolation of real-time threads. In Proceedings of the 7th IEEE International Workshop on Object-oriented Real-time Dependable Systems (San Diego, CA). 169-172.
18. BROOKS, D. M., BOSE, P., SCHUSTER, S. E., JACOBSON, H., KUDVA, P. N., BUYUKTOSUNOGLU, A., WELLMAN, J. D., ZYUBAN, V., GUPTA, M., AND COOK, P. W. 2000. Power-aware microarchitecture: designing and modeling challenges for next-generation microprocessors. IEEE Micro 20, 6, 26-44.
19. BURNS, J. AND GAUDIOT, J. L. 2002. SMT layout overhead and scalability. IEEE T. Parall. Distr. Syst. 13, 2, 142-155.
20. BUTLER, M., YEH, T. Y., PATT, Y. N., ALSUP, M., SCALES, H., AND SHEBANOW, M. 1991. Single instruction stream parallelism is greater than two. In Proceedings of the 18th International Symposium on Computer Architecture (Toronto, Ont., Canada). 276-286.
21. CHAPPELL, R. S., STARK, J., KIM, S. P., REINHARDT, S. K., AND PATT, Y. N. 1999. Simultaneous subordinate microthreading (SSMT). In Proceedings of the 26th Annual International Symposium on Computer Architecture (Atlanta, GA). 186-195.
22. CHRYSOS, G. Z. AND EMER, J. S. 1998. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture (Barcelona, Spain). 142-153.
23. CULLER, D. E., SINGH, J. P., AND GUPTA, A. 1998. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann, San Francisco, CA.
24. DALLY, W. J., FISKE, J., KEEN, J., LETHIN, R., NOAKES, M., NUTH, P., DAVISON, R., AND FYLER, G. 1992. The message-driven processor: a multicomputer processing node with efficient mechanisms. IEEE Micro 12, 2, 23-39.
25. DENNIS, J. B. AND GAO, G. R. 1994. Multithreaded architectures: principles, projects, and issues. In Multithreaded Computer Architecture: A Summary of the State of the Art, R. A. Iannucci, G. R. Gao, R. Halstead, and B. J. Smith, Eds. Kluwer Boston, MA, Dordrecht, The Netherlands, London, U.K. 1-74.
26. DOROJEVETS, M. 2000. COOL multithreading in HTMT SPELL-1 processors. Int. J. High Speed Electron. Sys. 10, 1, 247-253.
27. DOROZHEVETS, M. N. AND WOLCOTT, P. 1992. The El'brus-3 and MARS-M: recent advances in Russian high-performance computing. J. Supercomput. 6, 1, 5-48.
28. DUBEY, P. K., O'BRIEN, K., O'BRIEN, K. M., AND BARTON, C. 1995. Single-program speculative multithreading (SPSM) architecture: compiler-assisted fine-grain multithreading. Tech. Rep. RC 19928. IBM, Yorktown Heights, NY.
29. EGGERS, S. J., EMER, J. S., LEVY, H. M., LO, J. L., STAMM, R. M., AND TULLSEN, D. M. 1997. Simultaneous multithreading: a platform for next-generation processors. IEEE Micro 17, 5, 12-19.
30. EMER, J. S. 1999. Simultaneous multithreading: multiplying Alpha's performance. In Proceedings of the Microprocessor Forum (San Jose, CA).
31. ESPASA, R. AND VALERO, M. 1997. Exploiting instruction- and data-level parallelism. IEEE Micro 17, 5, 20-27.
32. FILLO, M., KECKLER, S. W., DALLY, W. J., CARTER, N. P., CHANG, A., AND GUREVICH, Y. 1995. The M-machine multicomputer. In Proceedings of the 28th Annual International Symposium on Microarchitecture (Ann Arbor, MI). 146-156.
33. FORMELLA, A., KELLER, J., AND WALLE, T. 1996. HPP: A high performance PRAM. In Lecture Notes in Computer Science, vol. 1123. Springer-Verlag, Heidelberg, Germany. 425-434.
34. FRANKLIN, M. 1993. The multiscalar architecture. Tech. Rep. 1196. Department of Computer Science, University of Wisconsin-Madison, Madison, WI.
35. FUHRMANN, S., PFEFFER, M., KREUZINGER, J., UNGERER, T., AND BRINKSCHULTE, U. 2001. Real-time garbage collection for a multithreaded Java microcontroller. In Proceedings of the 4th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (Magdeburg, Germany). 69-76.
36. GELINAS, B., HAYS, P., AND KATZMAN, S. 2002. Fine-grained hardware multi-threading: A CPU architecture for high-touch packed processing. Lexra Inc., Waltham, MA. White paper.
37. GLASKOWSKY, P. N. 2002. Network processors mature in 2001. Microproc. Report. February 19, 2002 (online journal).
38. GRÜNEWALD, W. AND UNGERER, T. 1996. Towards extremely fast context switching in a blockmultithreaded processor. In Proceedings of the 22nd Euromicro Conference (Prague, Czech Republic). 592-599.
39. GRÜNEWALD, W. AND UNGERER, T. 1997. A multithreaded processor designed for distributed shared memory systems. In Proceedings of the International Conference on Advances in Parallel and Distributed Computing (Shanghai, China). 206-213.
40. GULATI, M. AND BAGHERZADEH, N. 1996. Performance study of a multithreaded superscalar microprocessor. In Proceedings of the 2nd International Symposium on High-Performance Computer Architecture (San Jose, CA). 291-301.
41. GWENNAP, L. 1997. DanSoft develops VLIW design. Microproc. Report 11, 2 (Feb. 17), 18-22.
42. HALSTEAD, R. H. 1985. MULTILISP: a language for concurrent symbolic computation. ACM Trans. Program. Lang. Syst. 7, 4, 501-538.
43. HALSTEAD, R. H. AND FUJITA, T. 1988. MASA: a multithreaded processor architecture for parallel symbolic computing. In Proceedings of the 15th International Symposium on Computer Architecture (Honolulu, HI). 443-451.
44. HAMMOND, L. AND OLUKOTUN, K. 1998. Considerations in the design of Hydra: a multiprocessor-on-chip microarchitecture. Tech. Rep. CSL-TR-98-749. Computer Systems Laboratory, Stanford University, Stanford, CA.
45. HANSEN, C. 1996. MicroUnity's MediaProcessor architecture. IEEE Micro 16, 4, 34-41.
46. HIRATA, H., KIMURA, K., NAGAMINE, S., MOCHIZUM, Y., NISHIMURA, A., NAKASE, Y., AND NISHIZAWA, T. 1992. An elementary processor architecture with simultaneous instruction issuing from multiple threads. In Proceedings of the 19th International Symposium on Computer Architecture (Gold Coast, Australia). 136-145.
47. IANNUCCI, R. A., GAO, G. R., HALSTEAD, R., AND SMITH, B. J., Eds. 1994. Multithreaded Computer Architecture: A Summary of the State of the Art. Kluwer Boston, MA, Dordrecht, The Netherlands, London, U.K.
48. IBM CORPORATION. 1999. IBM network processor. Product overview. IBM, Yorktown Heights, NY.
49. INTEL CORPORATION. 2002. Intel Internet exchange architecture network processors: flexible, wire-speed processing from the customer premises to the network core. White paper. Intel, Santa Clara, CA.
50. JESSHOPE, C. R. 2001. Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. Aust. Comput. Sci. Commun. 23, 4, 80-88.
51. JESSHOPE, C. R. AND LUO, B. 2000. Micro-threading: a new approach to future RISC. In Proceedings of the Australasian Computer Architecture Conference (Canbera, Australia). 34-41.
52. KAVI, K. M., LEVINE, D. L., AND HURSON, A. R. 1997. A non-blocking multithreaded architecture. In Proceedings of the 5th International Conference on Advanced Computing (Madras, India). 171-177.
53. KLAUSER, A., AUSTIN, T., GRUNWALD, D., AND CALDER, B. 1998a. Dynamic hammock predication for non-predicated instruction sets. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Paris, France). 278-285.
54. KLAUSER, A., PAITHANKAR, A., AND GRUNWALD, D. 1998b. Selective eager execution on the PolyPath architecture. In Proceedings of the 25th Annual International Symposium on Computer Architecture (Barcelona, Spain). 250-259.
55. KREUZINGER, J., SCHULZ, A., PFEFFER, M., UNGERER, T., BRINKSCHULTE, U., AND KRAKOWSH, G. 2000. Real-time scheduling on multithreaded processors. In Proceedings of the 7th International Conference on Real-Time Computer Systems and Applications (Cheju Island, South Korea). 155-159.
56. KREUZINGER, J. AND UNGERER, T. 1999. Context-switching techniques for decoupled multithreaded processors. In Proceedings of the 25th Euromicro Conference (Milan, Italy). 1:248-251.
57. LAM, M. S. AND WILSON, R. P. 1992. Limits of control flow on parallelism. In Proceedings of the 18th International Symposium on Computer Architecture (Toronto, Ont., Canada). 46-57.
58. LAUDON, J., GUPTA, A., AND HOROWITZ, M. 1994. Interleaving: a multithreading technique targeting multiprocessors and workstations. In Proceedings of the 6th International Conference on Architectural Support for Programming Languages and Operating Systems (San Jose, CA). 308-318.
59. LAWSON, S. AND VANCE, A. 2002. Sun hints at UltraSparc V and beyond. Available online at PC World.com.
60. LI, Z., TSAI, J. Y., WANG, X., YEW, P. C., AND ZHENG, B. 1996. Compiler techniques for concurrent multithreading with hardware speculation support. In Lecture Notes in Computer Science, vol. 1239. Springer-Verlag, Heidelberg, Germany. 175-191.
61. LIPASTI, M. H. AND SHEN, J. P. 1997. The performance potential of value and dependence prediction. In Lecture Notes Computer Science, vol. 1300. Springer-Verlag, Heidelberg, Germany. 1043-1052.
62. LIPASTI, M. H., WILKERSON, C. B., AND SHEN, J. P. 1996. Value locality and load value prediction. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (Cambridge, MA). 138-147.
63. LO, J. L., BARROSO, L. A., EGGERS, S. J., GHARACHORLOO, K., LEVY, H. M., AND PAREKH, S. S. 1998. An analysis of database workload performance on simultaneous multithreaded processors. In Proceedings of the 25th Annual International Symposium on Computer Architecture (Barcelona, Spain). 39-50.
64. LO, J. L., EGGERS, S. J., EMER, J. S., LEW, H. M., STAMM, R. L., AND TULLSEN, D. M. 1997. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading. ACM Trans. Comput. Syst. 15, 3, 322-354.
65. LOIKKANEN, M. AND BAGHERZADEH, N. 1996. A fine-grain multithreading superscalar architecture. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Boston, MA). 163-168.
66. LÜTH, K., METZNER, A., PIEKENKAMP, T., AND RISU, J. 1997. The events approach to rapid prototyping for embedded control system. In Proceedings of the Workshop Zielarchitekturen, eingebetteter Syststeme (Rostock, Germany). 45-54.
67. MANKOVIC, T. E., POPESCU, V., AND SULLIVAN, H. 1987. CHoPP prieiples of operations. In Proceedings of the 2nd International Supercomputer Conference (Mannheim, Germany). 2-10.
68. MARCUELLO, P., GONZALES, A., AND TUBELLA, J. 1998. Speculative multithreaded processors. In Proceedings of the 12th International Conference on Supercomputing (Melbourne, Australia). 77-84.
69. MARK, D. T., BINNS, F., HILL, D. L., HINTON, G., KOUFATY, D. A., MILLER, J. A., AND UPTON, M. 2002. Hyper-threading technology architecture and microarchitecture: a hypertext history. Intel Technology J. 6, 1 (online journal).
70. METZNER, A. AND NIEHAUS, J. 2000. MSparc: multithreading in real-time architectures. J. Universal Comput. Sci. 6, 10, 1034-1051.
71. MIKSCHL, A. AND DAMM, W. 1996. Msparc: a multithreaded Spare. In Lecture Notes in Computer Science, vol. 1123. Springer-Verlag, Heidelberg, Germany. 461-469.
72. OEHRING, H., SIGMUND, U., AND UNGERER, T. 1999a. MPEG-2 video decompression on simultaneous multithreaded multimedia processors. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Newport Beach, CA). 11-16.
73. OEHRING, H., SIGMUND, U., AND UNGERER, T. 1999b. Simultaneous multithreading and multimedia. In Proceedings of the Workshop on Multithreaded Execution, Architecture and Compilation (Orlando, FL).
74. PATT, Y. N., PATEL, S. J., EVERS, M., FRIENDLY, D. H., AND STARK, J. 1997. One billion transistors, one uniprocessor, one chip. Computer 30, 9, 51-57.
75. PAUL, W. J., BACH, P., BOSCH, M., FISCHER, J., LICHTENAU, C., AND RÖHRIG, J. 2002. Real PRAM programming. In Lecture Notes in Computer Science, vol. 2400. Springer-Verlag, Heidelberg, Germany. 522-531.
76. PONTIUS, N. AND BAGHERZADEH, N. 1999. Multithreaded extensions enhance multimedia performance. In Proceedings of the Workshop on Multithreaded Execution, Architecture and Compilation (Orlando, FL).
77. ROTENBERG, E., JACOBSON, Q., SAZEIDES, Y., AND SMITH, J. E. 1997. Trace processors. In Proceedings of the 30th Annual International Symposium on Microarchitecture (Research Triangle Park, NC). 138-148.
78. RYCHLIK, B., FAISTL, J., KRUG, B., AND SHEN, J. P. 1998. Efficiency and performance impact of value prediction. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Paris, France). 148-154.
79. SENG, J. S., TULLSEN, D. M., AND CAI, G. Z. N. 2000. Power-sensitive multithreaded architecture. In Proceedings of the IEEE International Conference on Computer design: VLSI in Computers and Processors (Austin, TX). 199-206.
80. SERRANO, M. J., YAMAMOTO, W., WOOD, R., AND NEMIROVSKY, M. D. 1994. Performance estimation in a multistreamed superscalar processor. In Lecture Notes in Computer Science, vol. 794. Springer-Verlag, Heidelberg, Germany. 213-230.
81. SIGMUND, U., STEINHAUS, M., AND UNGERER, T. 2000. Transistor count and chip space assessment of multimedia-enhanced simultaneous multithreaded processors. In Proceedings of the 4th Workshop on Multithreaded Execution, Architecture and Compilation (Monterrey, CA).
82. SIGMUND, U. AND UNGERER, T. 1996a. Evaluating a multithreaded superscalar microprocessor versus a multiprocessor chip. In Proceedings of the 4th PASA Workshop on Parallel Systems and Algorithms (Jülich, Germany). 147-159.
83. SIGMUND, U. AND UNGERER, T. 1996b. Identifying bottlenecks in multithreaded superscalar multiprocessors. In Lecture Notes in Computer Science, vol. 1123. Springer-Verlag, Heidelberg, Germany. 797-800.
84. ŠILC, J., ROBIČ, B., AND UNGERER, T. 1998. Asynchrony in parallel computing: from dataflow to multithreading. Parall. Distr. Comput. Practices 1, 1, 57-83.
85. ŠILC, J., ROBIČ, B., AND UNGERER, T. 1999. Processor Architecture: From Dataflow to Superscalar and Beyond. Springer-Verlag, Heidelberg and Berlin, Germany, and New York, NY.
86. SMITH, B. J. 1981. Architecture and applications of the HEP multiprocessor computer system. SPIE Real-Time Signal Processing IV 298, 241-248.
87. SMITH, B. J. 1985. The architecture of hep. In Parallel MIMD Computation: HEP Supercomputer and Its Applications, J. S. Kowalik, Ed. MIT Press, Cambridge, MA, 41-55.
88. SMITH, J. E. AND VAJAPEYAM, S. 1997. Trace processors: moving to fourth-generation microarchitectures. Computer 30, 9, 68-74.
89. SOHI, G. S. 1997. Multiscalar: another fourth-generation processor. Computer 30, 9, 72.
90. SOHI, G. S. 2001. Microprocessors - 10 years back, 10 years ahead. In Lecture Notes in Computer Science, vol. 2000. Heidelberg, Germany. 208-218.
91. SOHI, G. S., BREACH, S. E., AND VIJAYKUJIAR, T. N. 1995. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on, Computer Architecture (Santa Margherita Ligure, Italy). 414-425.
92. STEINHAUS, M., KOLLA, R., LARRIBA-PEY, J. L., UNGERER, T., AND VALERO, M. 2001. Transistor count and chip space estimation of simple-scalar-based microprocessor models. In Proceedings of the Workshop on Complexity-Effective Design (Göteborg, Sweden).
93. STEALING, T. 1997. Beyond 100 teraflops through superconductors, holographic storage, and the data vortex. In Proceedings of the International Symposium on Supercomputing (Tokyo, Japan).
94. TENDLER, J. M., DODSON, J. S., FIELDS, JR., J. S., LE, H., AND SINHAROY, B. 2002. POWER4 system microarchitecture. IBM J. Res. Dev. 46, 1, 5-26.
95. TEXAS INSTRUMENTS. 1994. TMS320C80 Technical brief. Texas Instruments, Dallas, TX.
96. THISTLE, M. AND SMITH, B. J. 1988. A processor architecture for Horizon. In Proceedings of the Supercomputing Conference (Orlando, FL). 35-41.
97. TREMBLAY, M. 1999. A VLIW convergent multiprocessor system on a chip. In Proceedings of the Microprocessor Forum (San Jose, CA).
98. TREMBLAY, M., CHAN, J., CHAUDHRY, S., CONIGLIARO, A. W., AND TSE, S. S. 2000. The MAJC architecture: a synthesis of parallelism and scalability. IEEE Micro 20, 6, 12-25.
99. TSAI, J. Y. AND YEW, P. C. 1996. The super-threaded architecture: thread pipelining with run-time data dependence checking and control speculation. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Boston, MA). 35-46.
100. TULLSEN, D. M., EGGERS, S. J., EMER, J. S., LEVY, H. M., LO, J. L., AND STAMM, R. L. 1996. Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor. In Proceedings of the 23rd Annual International Symposium on Computer Architecture (Philadelphia, PA). 191-202.
101. TULLSEN, D. M., EGGERS, S. J., AND LEVY, H. M. 1995. Simultaneous multithreading: maximizing on-chip parallelism. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (Santa Margherita Ligure, Italy). 392-403.
102. TULLSEN, D. M., Lo, J. L., EGGERS, S. J., AND LEVY, H. M. 1999. Supporting fine-grained synchronization on a simultaneous multithreading processor. In Proceedings of the 5th International Symposium on High-Performance Computer Architecture (Orlando, FL). 54-58.
103. UNGERER, T., ROBIČ, B., AND ŠILC, J. 2002. Multithreaded processors. Computer J. 45, 3, 320-348.
104. VAJAPEYAM, S. AND MITRA, T. 1997. Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences. In Proceedings of the 24th Annual International Symposium on Computer Architecture (Denver, CO). 1-12.
105. VIJAYKUMAR, T. N. AND SOHI, G. S. 1998. Task selection for a multiscalar processor. In Proceedings of the 31st Annual International Symposium on Microarchitecture (Dallas, TX). 81-92.
106. WALL, D.W. 1991. Limits of instruction-level parallelism. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (Santa Clara, CA). 176-188.
107. WALLACE, S., CALDER, B., AND TULLSEN, D. M. 1998. Threaded multiple path execution. In Proceedings of the 25th Annual International Symposium on Computer Architecture (Barcelona, Spain). 238-249.
108. WALLACE, S., TULLSEN, D. M., AND CALDER, B. 1999. Instruction recycling on a multiple-path processor. In Proceedings of the 5th International Symposium on High-Performance Computer Architecture (Orlando, FL). 44-53.
109. WITTENBURG, J. P., MEYER, G., AND PIRSCH, P. 1999. Adapting and extending simultaneous multithreading for high performance video signal processing applications. In Proceedings of the Workshop on Multithreaded Execution, Architecture and Compilation (Orlando, FL).
110. YAMAMOTO, W. AND NEMIROVSKY, M. D. 1995. Increasing superscalar performance through multistreaming. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (Limassol, Cyprus). 49-58.