Instruction recycling on a multiple-path processor

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn , Issue , 1999, Pages 44-53

  Wallace, Steven ^a   Tullsen, Dean M ^a   Calder, Brad ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; MULTIPROGRAMMING; PIPELINE PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS);

INSTRUCTION RECYCLING; MULTIPLE-PATH PROCESSORS; SIMULTANEOUS MULTITHREADING ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0032777341     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/hpca.1999.744323     Document Type: Conference Paper

References (20)