The MAJC architecture: A synthesis of parallelism and scalability

IEEE Micro

Volumn 20, Issue 6, 2000, Pages 12-25

  Tremblay, Marc ^a,b,c   Chan, Jeffrey ^a,c,d   Chaudhry, Shailender ^a,d   Conigliaro, Andrew W ^a,c   Tse, Shing Sheung ^a,c  

^a SUN MICROSYSTEMS   (United States)

^b Processor and Products Group   (United States)

^c IEEE

^d MAJC Architecture Team ^*

Author keywords

[No Author keywords available]

Indexed keywords

DATA PROCESSING; JAVA PROGRAMMING LANGUAGE; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; MULTIPROGRAMMING; PROGRAM COMPILERS; RESOURCE ALLOCATION; SHIFT REGISTERS;

MICROPROCESSOR ARCHITECTURE OF JAVA COMPUTING; MULTITHREADING; PARALLELISM; VERY LONG INSTRUCTION WORD;

REDUCED INSTRUCTION SET COMPUTING;

EID: 0034316177     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.888700     Document Type: Article

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