Identifying bottlenecks in a multithreaded superscalar microprocessor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1124, Issue , 1996, Pages 797-800

  Sigmund, Ulrich ^a   Ungerer, Theo ^b  

^a VIONA Development GmbH   (Germany)

^b UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

EXECUTION UNITS; INSTRUCTIONS PER CYCLES; MULTITHREADED; SINGLE CYCLE; SUPERSCALAR MICRO-PROCESSORS; SUPERSCALAR PROCESSOR;

PARALLEL PROCESSING SYSTEMS;

EID: 84889036959     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0024779     Document Type: Conference Paper

References (4)

1. Tullsen, D. E., Eggers, S. J., Levy, H. M.: Simultaneous Multithreading: Maximizing On-Chip Parallelism. The 22nd Ann. Int. Symp. on Comp. Arch., (1995) 392-403
2. Song, S. P., Denman, M., Chang, J.: The PowerPC 604 RISC Microprocessor. IEEE Micro, Vol. 14, № 5 (1994) 8-17
3. Sigmund, U., Ungerer, Th.: Evaluating a Multithreaded Superscalar Microprocessor vs. a Multiprocessor Chip. 4th PASA Workshop, Juelich, World Sc. Publ. (1996)
4. Hennessy, J. L., Patterson, D. A.: Computer Architecture a Quantitative Approach, San Mateo (1996)