Exploiting instrucion- and data-level parallelism

IEEE Micro

Volumn 17, Issue 5, 1997, Pages 20-27

  Espasa, Roger ^a   Valero, Mateo ^a,b,c,d,e,f  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

^c UNIVERSITY OF BARCELONA   (Spain)

^d IEEE

^e Catalan Ctr Computation and Commun   (Spain)

^f Catalan Ctr Computation and Commun ^*  (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; MULTIPROGRAMMING; STORAGE ALLOCATION (COMPUTER); TRANSISTORS;

DATA LEVEL PARALLELISM; INSTRUCTION LEVEL PARALLELISM; SIMULTANEOUS MULTITHREADED VECTOR (SMT);

MICROPROCESSOR CHIPS;

EID: 0031238147     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.621210     Document Type: Article

References (13)

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