Compiler techniques for concurrent multithreading with hardware speculation support

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1239, Issue , 1997, Pages 175-191

  Li, Zhiyuan ^a   Tsai, Jenn Yuan ^a   Wang, Xin ^b   Yew, Pen Chung ^b   Zheng, Bess ^b  

^a University of Illinois at Urbana Champaign   (United States)

^b UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; HARDWARE; MULTITASKING; PROGRAM COMPILERS; PROGRAM PROCESSORS; RECONFIGURABLE HARDWARE;

COMPILER TECHNIQUES; DATA DEPENDENCE; MULTI-THREADING; MULTITHREADING ARCHITECTURES; PARALLELIZATIONS; RUN-TIME DATA; WHILE LOOPS;

CONCURRENCY CONTROL;

EID: 84957692552     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/BFb0017252     Document Type: Conference Paper

References (12)

1. Randy Allen and Steve Johnson. Compiler C for vectorization, parallelization, and inline expansion. In Prof, of SIGPLAN '88 Conference on Programming Language Design and Implementation, pages 241-249, June 1988.
2. Pradeep K. Dubey, Kevin O'Brien, Kathryn O'Brien, and Charles Barton. Single-program speculative multithreading (SPSM) architecture: Compiler-assisted finegrained multithreading. In Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT '95, pages 109-121, June 27-29, 1995.
3. Manoj Franklin and Gurindar S. Sohi. The expandable split window paradigm for exploiting fine-grained parallelism. In Proceedings of the 19th Annual International Symposium on Computer Architecture, pages 58-67, May 19-21, 1992.
4. M. Girkar and C. Polychronopoulos. The HTG: An intermediate representation for programs based on control and data dependences. CSRD Technical Report No. 1046, Univ. of Illinois at Urbana-Champaign, 1991.
5. Justiani, and L J. Hendren. Supporting array dependence testing for an optimizing/parallelizing c compiler. In Proc. of the 1994 International Conference on Compiler Construction. Volume 749 of Lecture Notes in Computer Science. Springer Verlag, April 1994.
6. Z. Li. Compiler algorithms for event variable synchronization. In Proc. of the Fifth International Conference on Supercomputing (ACM), June 1991.
7. D.E. Maydan, S.P. Amarasinghe, and M.S. Lam. Array data-flow analysis and its use in array privatization. In Proc. of the 20th ACM Symp. on Principles of Programming Languages, pages 2-15, January 1993.
8. S. P. Midkiff and D. A. Padua. Compiler algorithms for synchronization. IEEE Transactions on Computers, C-3612:1485-1495, December 1987.
9. Andreas I. Moshovos, Scott E. Breach, T. N. Vijaykumar, and Guri. S. Sohi. Submitted for a blind review to a conference.
10. B. A. Nayfeh and K. Olukotun. Exploring the design space for a shared-cache multiprocessor. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 166-175, April 1994.
11. Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar. Multiscalar processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, pages 414-425, June 22-24, 1995.
12. Jenn-Yuan Tsai and Pen-Chung Yew. The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation. In Proceedings of International Conference on Parallel Architectures and Compilation Techniques, PACT '96, October 1996.