Multithreaded processors

Computer Journal

Volumn 45, Issue 3, 2002, Pages 320-348

  Ungerer, Theo ^a   Robič, Borut ^b   Šilc, Jurij ^c  

^a UNIVERSITY OF AUGSBURG   (Germany)

^b UNIVERSITY OF LJUBLJANA   (Slovenia)

^c JO EF STEFAN INSTITUTE   (Slovenia)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; MULTIPLEXING; MULTIPROGRAMMING; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; THROUGHPUT;

MULTITHREADED PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0036267893     PISSN: 00104620     EISSN: None     Source Type: Journal    
DOI: 10.1093/comjnl/45.3.320     Document Type: Article

References (132)

1. One billion transistors, one uniprocessor, one chip
2. A survey of new research directions in microprocessors
3. Limits of control flow on parallelism
4. Limits of instruction-level parallelism
5. Single instruction stream parallelism is greater than two
6. Superspeculative microarchitecture for beyond AD 2000
7. Memory dependence prediction using store sets
8. The performance potential of value and dependence prediction
9. Value locality and load value prediction
10. Efficiency and performance impact of value prediction
11. Architecture and applications of the HEP multiprocessor computer system
12. Execution characteristics of desktop applications on Windows NT
13. Speculative multithreaded processor
14. The multiscalar architecture
15. Multiscalar: Another fourth-generation processor
16. Multiscalar processors
17. Task selection for a multiscalar processor
18. Trace processors
19. Trace processors: Moving to fourth-generation microarchitectures
20. Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
21. Single-program speculative multithreading (SPSM) architecture: Compiler-assisted fine-grain multithreading
22. Compiler techniques for concurrent multithreading with hardware speculation support
23. The superthreaded architecture: Thread pipelining with run-time data dependence checking and control speculation
24. A dynamic multithreading processor
25. Speculative multithreaded processors
26. Dynamic hammock predication for non-predicated instruction sets
27. Selective eager execution on the PolyPath architecture
28. Simultaneous subordinate microthreading (SSMT)
29. Memory system characterization of commercial workloads
30. The Tera computer system
31. Multithreaded architectures: Principles, projects, and issues
32. Asynchrony in parallel computing: From dataflow to multithreading
33. Simultaneous multithreading: A platform for next-generation processors
34. Interleaving: A multithreading technique targeting multiprocessors and workstations
35. The architecture of HEP
36. A processor architecture for horizon
37. MASA: A multi-threaded processor architecture for parallel symbolic computing
38. HPP: A high performance PRAM
39. MicroUnity's MediaProcessor architecture
40. Scheduling on the Tera MTA
41. The M-machine multicomputer
42. Building the 4 processor SB-PRAM prototype
43. Beyond 100 teraflops through superconductors, holographic storage, and the data vortex
44. COOL multithreading in HTMT SPELL-1 processors
45. Context-switching techniques for decoupled multithreaded processors
46. Improved multithreading techniques for hiding communication latency in multi-processors
47. Sparcle: An evolutionary processor design for large-scale multiprocessors
48. Msparc: A multithreaded Sparc
49. CHoPP principles of operations
50. Towards extremely fast context switching in a block multithreaded processor
51. A multithreaded processor designed for distributed shared memory systems
52. The message-driven processor: A multicomputer processing node with efficient mechanisms
53. The MIT Alewife machine: Architecture and performance
54. A non-blocking multithreaded architecture
55. DanSoft develops VLIW design
56. Dynamic scheduling in RISC architectures
57. Micro-threading: A new approach to future RISC
58. Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines
59. A VLIW convergent multiprocessor system on a chip
60. The MAJC architecture: A synthesis of parallelism and scalability
61. A multithreaded PowerPC processor for commercial servers
62. The El'brus-3 and MARS-M: Recent advances in Russian high-performance computing
63. An elementary processor architecture with simultaneous instruction issuing from multiple threads
64. Performance estimation in a multi-streamed superscalar processor
65. Increasing superscalar performance through multistreaming
66. Performance study of a multithreaded superscalar microprocessor
67. A fine-grain multithreading superscalar architecture
68. Multithreaded extensions enhance multimedia performance
69. Simultaneous multithreading: Maximizing on-chip parallelism
70. Exploiting choice: Instruction fetch and issue on an implementable simultaneous multi-threading processor
71. Converting thread-level parallelism to instruction-level parallelism via simultaneous multithreading
72. Supporting fine-grained synchronization on a simultaneous multithreading processor
73. Threaded multiple path execution
74. Instruction recycling on a multiple-path processor
75. An analysis of database workload performance on simultaneous multithreaded processors
76. Power-sensitive multithreaded architecture
77. Evaluating a multi-threaded superscalar microprocessor versus a multiprocessor chip
78. Identifying bottlenecks in multithreaded superscalar multiprocessors
79. MPEG-2 video decompression on simultaneous multithreaded multimedia processors
80. Performance of simultaneous multithreaded multimedia-enhanced processors for MPEG-2 video decompression
81. Transistor count and chip space assessment of multimedia-enhanced simultaneous multithreaded processors
82. Transistor count and chip space estimation of simple-scalar-based microprocessor models
83. Quantifying the SMT layout overhead - Does SMT pull its weight?
84. Exploiting instruction- and data-level parallelism
85. Simultaneous multithreading: Multiplying Alpha's performance
86. Blue Gene: A vision for protein science using a petaflops supercomputer
87. Speculative versioning cache
88. Trace cache: A low latency approach to high bandwidth instruction fetch
89. Control speculation in multithreaded processors through dynamic loop detection
90. On dynamic speculative thread partitioning and the MEM-slicing algorithm
91. Concurrent event handling through multithreading
92. The use of multithreading for exception handling
93. Execution-based prediction using speculative slices
94. Speculative precomputation: Long-range prefetching of delinquent loads
95. Tolerating memory latency through software-controlled pre-execution in simultaneous multi-threading processors
96. An empirical study of decentralized ILP execution models
97. Execution and cache performance of the Scheduled dataflow architecture
98. A compiler technique for speculative execution of alternative program paths targeting multithreaded architectures
99. Static speculation, dynamic resolution
100. Compiler supported speculative execution on SMT processors
101. Simultaneous speculation scheduling
102. Disjoint eager execution: An optimal form of speculative execution
103. Assigning confidence to control conditional branch predictions
104. Adapting and extending simultaneous multithreading for high performance video signal processing applications
105. MSPARC: Multithreading in real-time architectures
106. The events approach to rapid prototyping for embedded control system
107. A multithreaded Java micro-controller for thread-oriented real-time event-handling
108. The Komodo project: Thread-based event handling supported by a multithreaded Java microcontroller
109. Real-time scheduling on multithreaded processors
110. A microkernel middleware architecture for distributed embedded real-time systems
111. Real-time garbage collection for a multithreaded Java microcontroller
112. Evaluation of design alternatives for a multiprocessor microprocessor
113. The case for a single-chip multiprocessor
114. Power4 focuses on memory bandwidth
115. Single-chip H.324 videoconferencing
116. Data speculation support for a chip multiprocessor
117. The circuit and physical design of the POWER4 microprocessor
118. A single-chip multiprocessor
119. A clustered approach to multithreaded processors
120. Microprocessors - 10 years back, 10 years ahead
121. MAJC-5200: A high performance microprocessor for multimedia computing