Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines

Proceedings of the Australasian Computer Systems Architecture Conference, ACSAC

Volumn 2001-January, Issue , 2001, Pages 80-88

  Jesshope, C ^a  

^a MASSEY UNIVERSITY   (New Zealand)

Author keywords

Delay; Hardware; History; Logic; Microprocessors; Parallel processing; Pipelines; Processor scheduling; Supercomputers; Yarn

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ECONOMIC AND SOCIAL EFFECTS; EMBEDDED SYSTEMS; HISTORY; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARALLEL PROCESSING SYSTEMS; PIPELINES; SUPERCOMPUTERS; VECTORS; YARN;

CHIP MULTI-PROCESSORS; DELAY; INSTRUCTION LEVEL PARALLELISM; LOGIC; MEMORY LATENCIES; PARALLEL PROCESSING; PROCESSOR SCHEDULING; VECTOR SUPERCOMPUTERS;

PIPELINE PROCESSING SYSTEMS;

EID: 84949521500     PISSN: 15300927     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACAC.2001.903363     Document Type: Conference Paper

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