Superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1996, Pages 35-46

  Tsai, Jenn Yuan ^a   Yew, Pen Chung ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; DATA STORAGE EQUIPMENT; DATA STRUCTURES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS);

CONTROL SPECULATION; MEMORY WRITE BACKS; RUNTIME DATA DEPENDENCE CHECKING; SUPERTHREADED ARCHITECTURE; THREAD PIPELINING;

COMPUTER ARCHITECTURE;

EID: 0029727822     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)