Asynchronous on-chip networks

IEE Proceedings: Computers and Digital Techniques

Volumn 152, Issue 2, 2005, Pages 273-283

  Amde, M ^a   Felicijan, T ^b   Efthymiou, A ^b   Edwards, D ^b   Lavagno, L ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF MANCHESTER   (United Kingdom)

^c POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER PROGRAMMING; DATA ACQUISITION; NETWORK PROTOCOLS; SIGNAL INTERFERENCE;

ASYNCHRONOUS DESIGN; CLOCK POWER CONSUMPTION; CLOCK SKEW; SYNCHRONOUS ON-CHIP NETWORKS;

MICROPROCESSOR CHIPS;

EID: 19344376277     PISSN: 13502387     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cdt:20045093     Document Type: Conference Paper

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