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Volumn 10, Issue , 2004, Pages 149-158

Handshake protocols for de-synchronization

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATION; COMPUTER AIDED DESIGN; CONCURRENT ENGINEERING; CONTROL EQUIPMENT; INFORMATION ANALYSIS; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); OPTIMIZATION; SPECIFICATIONS; SYNCHRONIZATION;

EID: 2942633331     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper
Times cited : (65)

References (23)
  • 1
    • 0002686471 scopus 로고    scopus 로고
    • Compiling the language Balsa to delay-insensitive hardware
    • C. D. Kloos and E. Cerny, editors, Apr.
    • A. Bardsley and D. Edwards. Compiling the language Balsa to delay-insensitive hardware. In C. D. Kloos and E. Cerny, editors, Hardware Description Languages and their Applications (CHDL), pages 89-91, Apr. 1997.
    • (1997) Hardware Description Languages and Their Applications (CHDL) , pp. 89-91
    • Bardsley, A.1    Edwards, D.2
  • 8
    • 0030173207 scopus 로고    scopus 로고
    • Four-phase micropipeline latch control circuits
    • June
    • S. B. Furber and P. Day. Four-phase micropipeline latch control circuits. IEEE Transactions on VLSI Systems, 4(2):247-253, June 1996.
    • (1996) IEEE Transactions on VLSI Systems , vol.4 , Issue.2 , pp. 247-253
    • Furber, S.B.1    Day, P.2
  • 15
    • 0030244752 scopus 로고    scopus 로고
    • Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry
    • Sept.
    • D. H. Linder and J. C. Harden. Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry. IEEE Transactions on Computers, 45(9):1031-1044, Sept. 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.9 , pp. 1031-1044
    • Linder, D.H.1    Harden, J.C.2
  • 16
    • 0022879965 scopus 로고
    • Compiling communicating processes into delay-insensitive VLSI circuits
    • A. J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits. Distributed Computing, 1(4):226-234, 1986.
    • (1986) Distributed Computing , vol.1 , Issue.4 , pp. 226-234
    • Martin, A.J.1
  • 18
    • 0024645936 scopus 로고
    • Petti Nets: Properties, analysis and applications
    • Apr.
    • T. Murata, Petti Nets: Properties, analysis and applications, proceedings of the IEEE, pages 541-580, Apr. 1989.
    • (1989) Proceedings of the IEEE , pp. 541-580
    • Murata, T.1
  • 21
    • 0035186879 scopus 로고    scopus 로고
    • MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines
    • Nov.
    • M. Singh and S. M. Nowick. MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines. In Proc. International Conf. Computer Design (ICCD), pages 9-17, Nov. 2001.
    • (2001) Proc. International Conf. Computer Design (ICCD) , pp. 9-17
    • Singh, M.1    Nowick, S.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.