Multi-GHz clocking scheme for Intel® Pentium® 4 microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 404-405

  Kurd, N A ^a   Barkatullah, J S ^a   Dizon, R O ^a   Fletcher, T D ^a   Madland, P D ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC CLOCKS; INPUT OUTPUT PROGRAMS; JITTER; OPTIMIZATION; PHASE LOCKED LOOPS; SYNCHRONIZATION; VARIABLE FREQUENCY OSCILLATORS;

CORE CLOCK FREQUENCY; DOMAIN DESKEW REGISTERS (DDR);

MICROPROCESSOR CHIPS;

EID: 0035060749     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Clock generation and distribution for the first IA-64 microprocessor