Automatic scan insertion and pattern generation for asynchronous circuits

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 672-673

  Efthymiou, Aristides ^a   Sotiriou, Christos ^b   Edwards, Douglas ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b INSTITUTE OF COMPUTER SCIENCE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; AUTOMATIC SCAN INSERTION; INDUSTRIAL QUALITY TESTABILITY; PIPELINE LATCHES; CLOCKING SCHEMES; FEEDBACK PATHS; GLOBAL CIRCUIT; INDUSTRIAL QUALITY; INTERCONNECTION FABRICS; PATTERN GENERATION; TEST COVERAGE;

ASYNCHRONOUS SEQUENTIAL LOGIC; ELECTRIC NETWORK ANALYSIS; EVALUATION; INTERCONNECTION NETWORKS; LOGIC GATES; TESTING; EXHIBITIONS; FEEDBACK;

COMBINATORIAL CIRCUITS; ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 3042520860     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268924     Document Type: Conference Paper

References (2)

1. K. van Berkel, A. Peeters, and F. te Beest. Adding synchronous and LSSD modes to asynchronous circuits. In ASYNC02, pages 146-155, Apr. 2002.
2. W. J. Bainbridge and S. B. Furber. CHAIN: A delay insensitive CHip area INterconnect. IEEE Micro, 22(5): 16-23, Sept/Oct 2002.