Polychrony for formal refinement-checking in a system-level design methodology

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 2003-January, Issue , 2003, Pages 9-19

  Talpin, Jean Pierre ^a   Le Guernic, Paul Le ^a   Shukla, Sandeep Kumar ^b   Gupta, Rajesh ^c   Doucet, Frédéric ^c  

^a CAMPUS DE BEAULIEU   (France)

^b Virgina Tech ^*  (France)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Concurrent computing; System level design

Indexed keywords

ABSTRACTING; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; HIGH LEVEL LANGUAGES; HIGH LEVEL SYNTHESIS; INTEGRATED CIRCUIT DESIGN; MICROPROCESSOR CHIPS; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

BEHAVIORAL SYNTHESIS; CONCURRENT COMPUTING; CONFORMANCE CHECKING; DESIGN ABSTRACTIONS; SUCCESSIVE REFINEMENT; SYSTEM LEVEL DESIGN; SYSTEM LEVEL DESIGN LANGUAGES; SYSTEM ON CHIP DESIGN;

LOGIC DESIGN;

EID: 51949110466     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.2003.1207695     Document Type: Conference Paper

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