Multiclock ESTEREL: A reactive framework for asynchronous design

Proceedings of the International Parallel Processing Symposium, IPPS

Volumn , Issue , 2000, Pages 201-209

  Rajan, Basant ^a   Shyamasundar, R K ^a  

^a TATA INSTITUTE OF FUNDAMENTAL RESEARCH   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FLIP FLOP CIRCUITS; MATHEMATICAL MODELS; TIMING CIRCUITS;

MULTICLOCK ESTEREL PROGRAMMING LANGUAGE;

COMPUTER PROGRAMMING LANGUAGES;

EID: 0033890921     PISSN: 10637133     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)