Data communication in systems with heterogeneous timing

IEEE Micro

Volumn 22, Issue 6, 2002, Pages 58-69

  Xia, Fei ^a   Yakovlev, Alex V ^a   Clark, Ian G ^a   Shang, Delong ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER NETWORKS; COMPUTER SIMULATION; DATA TRANSFER; DISTRIBUTED COMPUTER SYSTEMS; EMBEDDED SYSTEMS; INFORMATION TECHNOLOGY; NETWORK PROTOCOLS; PETRI NETS; REAL TIME SYSTEMS; USER INTERFACES; VLSI CIRCUITS;

ASYNCHRONOUS COMMUNICATION MECHANISMS; HETEROGENEOUSLY TIMED NETWORKS;

DATA COMMUNICATION SYSTEMS;

EID: 0036871555     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2002.1134344     Document Type: Article

References (14)

1. L. Lamport, "On Interprocess Communication: Parts I and II," Distributed Computing, vol. 1, no. 2, pp. 77-101.
2. H.R. Simpson, "Four-Slot Fully Asynchronous Communication Mechanism," IEE Proc., vol. 137, no. 1, Jan. 1990, pp. 17-30.
3. H.R. Simpson and E. Campbell, "Real-Time Network Architecture: Principles and Practice," Proc. Asynchronous Interfaces: Tools, Techniques and Implementations (AINT 00), Technische Universiteit Delft, the Netherlands, 2000, p. 5 and handouts.
4. D.M. Chapiro, Globally-Asynchronous Locally-Synchronous Systems, doctoral dissertation, Dept. of Computer Science, Stanford Univ., Palo Alto, Calif., 1986.
5. K.Y. Yun, and A.E. Dooply, "Pausible Clocking Based Heterogeneous Systems," IEEE Trans. Very Large-Scale Integration (VLSI) Systems, vol. 7, no. 4, Dec. 1999, pp. 482-488.
6. T. Chelcea and S.M. Nowick, "Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols," Proc. 38th Design Automation Conf. (DAC 01), ACM Press, New York, 2001, pp. 21-26.
7. L.P. Carloni, K.L. McMillan, and A.L. Sangiovanni-Vincentelli, "The Theory of Latency Insensitive Design," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, IEEE Press, Piscataway, N.J., 2001, pp. 1059-1076.
8. J.L. Peterson, Petri Net Theory and the Modelling of Systems, Prentice-Hall, Upper Saddle River, N.J., 1981.
9. F. Xia et al., "Asynchronous Communication Mechanisms Using Self-Timed Circuits," Proc. 6th Int'l Symp. Advanced Research Asynchronous Circuits and Systems (ASYNC 00), IEEE CS Press, Los Alamitos, Calif., 2000, pp. 150-159.
10. A. Yakovlev, F. Xia, and D. Shang, "Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism," Proc. 7th Int'l Symp. Asynchronous Circuits and Systems (ASYNC 01), IEEE CS Press, Los Alamitos, Calif. 2001, pp. 127-136.
11. F. Xia and I. Clark, "Algorithms for Signal and Message Asynchronous Communication Mechanisms and Their Analysis," Proc. 2nd Int'l Conf. Applications of Concurrency to System Design (ACSD 01), IEEE CS Press, Los Alamitos, Calif., 2001, pp. 65-74.
12. D. Shang, F. Xia, and A. Yakovlev, "Asynchronous Circuit Synthesis via Direct Translation," Proc. Int'l Symp. Circuits and Systems (ISCAS 02), IEEE Press, Piscataway, N.J. 2002, pp. 369-372.
13. D. Shang, F. Xia, and A. Yakovlev, "Testing a Self-Timed Asynchronous Communication Mechanism (ACM) VLSI Chip," IEEE Workshop Design and Diagnostics of Electronic Circuits and Systems (DDECS 01), IEEE Press, Piscataway, N.J., 2001, pp. 53-56.
14. A. Madalinski, F. Xia, and A. Yakovlev, "Studying the Data Loss and Data Re-Reading Behaviour of a Four-Slot ACM Using SPN Techniques," Proc. 7th UK Async Forum, 1999; http://www.cs.man.ac.uk/async/events/ukforum.html.