Nanoelectronic architectures

Applied Physics A: Materials Science and Processing

Volumn 80, Issue 6, 2005, Pages 1183-1195

  Snider, G ^a   Kuekes, P ^a   Hogg, T ^a   Williams, R Stanley ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; CROSSBAR EQUIPMENT; LITHOGRAPHY; LOGIC GATES; MICROPROCESSOR CHIPS; NANOSTRUCTURED MATERIALS; SEMICONDUCTOR DIODES; TRANSISTORS;

LATCHING MECHANSIMS; NANOELECTRONIC ARCHITECTURE; NANOIMPRINT LITHOGRAPHY; NANOWIRES;

NANOTECHNOLOGY;

EID: 16244364411     PISSN: 09478396     EISSN: None     Source Type: Journal    
DOI: 10.1007/s00339-004-3154-4     Document Type: Article

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