-
1
-
-
0024628592
-
Self-Exercising Checkers for Unified Built-In Self-Test (UBIST)
-
March
-
M. Nicolaidis, "Self-Exercising Checkers for Unified Built-In Self-Test (UBIST)," IEEE Trans. on Computer Aided-Design, Vol. 8, No. 3, pp. 203-218, March 1989.
-
(1989)
IEEE Trans. on Computer Aided-design
, vol.8
, Issue.3
, pp. 203-218
-
-
Nicolaidis, M.1
-
3
-
-
0019912702
-
The Design of PLAs with Concurrent Error Detection
-
June
-
G.P. Mak, J.A. Abraham, and E.S. Davidson, "The Design of PLAs with Concurrent Error Detection," Proc. FTCS, June 1982, pp. 303-310.
-
(1982)
Proc. FTCS
, pp. 303-310
-
-
Mak, G.P.1
Abraham, J.A.2
Davidson, E.S.3
-
4
-
-
0026263523
-
New Implmentations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead
-
Oct.
-
M. Nicolaidis and M. Boudjit, "New Implmentations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead," Proc. of International Conference on Computer Design, Oct. 1991, pp. 275-281.
-
(1991)
Proc. of International Conference on Computer Design
, pp. 275-281
-
-
Nicolaidis, M.1
Boudjit, M.2
-
5
-
-
0343950683
-
-
Prentice-Hall, Englewood Cliffs, NJ, Chap. 5
-
D.K. Pradhan, Fault Tolerant Computing: Theory and Techniques, Prentice-Hall, Englewood Cliffs, NJ, 1986, Vol. 1, Chap. 5.
-
Fault Tolerant Computing: Theory and Techniques
, vol.1986
, pp. 1
-
-
Pradhan, D.K.1
-
6
-
-
0026852547
-
An SFS Berger Check Prediction ALU and Its Application to Self-Checking Processor Designs
-
April
-
J.-C. Lo, S. Thanawastein, and M. Nicolaidis, "An SFS Berger Check Prediction ALU and Its Application to Self-Checking Processor Designs," IEEE Trans. on Computer Aided-Design, Vol. 11, No. 4, pp. 525-540, April 1992.
-
(1992)
IEEE Trans. on Computer Aided-design
, vol.11
, Issue.4
, pp. 525-540
-
-
Lo, J.-C.1
Thanawastein, S.2
Nicolaidis, M.3
-
7
-
-
0029716420
-
A Self-Checking ALU Design with Efficient Codes
-
April
-
S. Gorshe and B. Bose, "A Self-Checking ALU Design with Efficient Codes," Proc. of VLSI Test Symposium, April 1996, pp. 157-161.
-
(1996)
Proc. of VLSI Test Symposium
, pp. 157-161
-
-
Gorshe, S.1
Bose, B.2
-
9
-
-
0003035229
-
A Note on Error Detecting Codes for Asymmetric Channels
-
March
-
J.M. Berger, "A Note on Error Detecting Codes for Asymmetric Channels," Information and Control, Vol. 4, pp. 68-73, March 1961.
-
(1961)
Information and Control
, vol.4
, pp. 68-73
-
-
Berger, J.M.1
-
10
-
-
0027610679
-
Design and Synthesis of Self-Checking VLSI Circuits
-
June
-
N.K. Jha and S. Wang, "Design and Synthesis of Self-Checking VLSI Circuits," IEEE Trans. Computer-Aided Design, Vol. 12, No. 6, pp. 878-887, June 1993.
-
(1993)
IEEE Trans. Computer-aided Design
, vol.12
, Issue.6
, pp. 878-887
-
-
Jha, N.K.1
Wang, S.2
-
11
-
-
33747834679
-
MIS: A Multiple-Level Logic Optimization System
-
Nov.
-
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, "MIS: A Multiple-Level Logic Optimization System," IEEE Trans. on Computer Aided-Design, Vol. 6, pp. 1062-1081, Nov. 1987.
-
(1987)
IEEE Trans. on Computer Aided-design
, vol.6
, pp. 1062-1081
-
-
Brayton, R.K.1
Rudell, R.2
Sangiovanni-Vincentelli, A.3
Wang, A.R.4
-
12
-
-
0343078816
-
Break Faults in Circuits with Parity Prediction
-
Center for Reliable Computing, Stanford University, Stanford, CA, Dec.
-
B. Khodadad-Mostashiry, "Break Faults in Circuits with Parity Prediction," Technical Note No. 183, Center for Reliable Computing, Stanford University, Stanford, CA, Dec. 1980.
-
(1980)
Technical Note No. 183
, vol.183
-
-
Khodadad-Mostashiry, B.1
-
13
-
-
0028457094
-
RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits
-
June
-
K. De, C. Natarajan, D. Nair, and P. Banerjee, "RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits," IEEE Trans. VLSI Systems, pp. 186-195, June 1994.
-
(1994)
IEEE Trans. VLSI Systems
, pp. 186-195
-
-
De, K.1
Natarajan, C.2
Nair, D.3
Banerjee, P.4
-
14
-
-
0022147652
-
Systematic Unidirectional Error-Detecting Codes
-
Nov.
-
B. Bose and D.J. Lin, "Systematic Unidirectional Error-Detecting Codes," IEEE Trans. on Computer Aided-Design, Vol. C-34, No. 11, pp. 1024-1032, Nov. 1985.
-
(1985)
IEEE Trans. on Computer Aided-design
, vol.C-34
, Issue.11
, pp. 1024-1032
-
-
Bose, B.1
Lin, D.J.2
-
15
-
-
0003582752
-
Design of Self-Checking Digital Networks Using Coding Techniques
-
Coordinated Science Laboratory, University of Illinois, Urbana, IL
-
D.A. Anderson, "Design of Self-Checking Digital Networks Using Coding Techniques," Technical Report R-527, Coordinated Science Laboratory, University of Illinois, Urbana, IL, 1971.
-
(1971)
Technical Report R-527
-
-
Anderson, D.A.1
-
16
-
-
0017982079
-
Strongly Fault Secure Logic Networks
-
June
-
J.E. Smith and G. Metze, "Strongly Fault Secure Logic Networks," IEEE Trans. Computers, Vol. C-27, No. 6, pp. 491-499, June 1978.
-
(1978)
IEEE Trans. Computers
, vol.C-27
, Issue.6
, pp. 491-499
-
-
Smith, J.E.1
Metze, G.2
-
17
-
-
0025839556
-
Totally Self-CheckingChecker Designs for Bose-Lin, Bose and Blaum Codes
-
Jan.
-
N.K. Jha, "TotallySelf-CheckingChecker Designs for Bose-Lin, Bose and Blaum Codes," IEEE Trans. Computer-Aided Design, Vol. 10, No. 1, pp. 136-143, Jan. 1991.
-
(1991)
IEEE Trans. Computer-aided Design
, vol.10
, Issue.1
, pp. 136-143
-
-
Jha, N.K.1
-
18
-
-
0018058113
-
Design of Self-Checking Checkers for Berger Codes
-
June
-
M.A. Marouf and A.D. Friedman, "Design of Self-Checking Checkers for Berger Codes," Proc. FTCS, June 1978, pp. 179-184.
-
(1978)
Proc. FTCS
, pp. 179-184
-
-
Marouf, M.A.1
Friedman, A.D.2
-
19
-
-
0031998141
-
A New Design Method for Self-Checking Unidirectional Combinational Circuits
-
Feb.
-
V.V. Saposhnikov, A. Morosov, VL. V. Saposhnikov, and M. Goessel, "A New Design Method for Self-Checking Unidirectional Combinational Circuits," JETTA, Vol. 12, Issue 1/2pp. 41-53, Feb. 1998.
-
(1998)
JETTA
, vol.12
, Issue.1-2
, pp. 41-53
-
-
Saposhnikov, V.V.1
Morosov, A.2
Saposhnikov, Vl.V.3
Goessel, M.4
-
20
-
-
0023210698
-
Dagon: Technology Binding and Local Optimization by DAG Matching
-
June
-
K. Keutzer, "Dagon: Technology Binding and Local Optimization by DAG Matching," Proc. IEEE/ACM 24th Design Automation Conf., June 1987, pp. 341-347.
-
(1987)
Proc. IEEE/ACM 24th Design Automation Conf.
, pp. 341-347
-
-
Keutzer, K.1
-
21
-
-
0023559691
-
Technology Mapping in MIS
-
Nov.
-
E. Detjens, G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "Technology Mapping in MIS," Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), Nov. 1987, pp. 116-119.
-
(1987)
Proc. IEEE/ACM Int. Conf. Computer-aided Design (ICCAD)
, pp. 116-119
-
-
Detjens, E.1
Gannot, G.2
Rudell, R.3
Sangiovanni-Vincentelli, A.4
Wang, A.5
-
22
-
-
0024168714
-
MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations
-
Dec.
-
S. Devadas, Ma Hi-Keung, A.R. Newton, and A. Sangiovanni-Vincentelli, "MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations," IEEE Trans. on Computer Aided-Design, Vol. 7, No. 12, pp. 1290-1299, Dec. 1988.
-
(1988)
IEEE Trans. on Computer Aided-design
, vol.7
, Issue.12
, pp. 1290-1299
-
-
Devadas, S.1
Ma, H.-K.2
Newton, A.R.3
Sangiovanni-Vincentelli, A.4
|