Algorithm level recomputing using allocation diversity: A register transfer level approach to time redundancy-based concurrent error detection

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 9, 2002, Pages 1077-1087

  Wu, Kaijie ^a,b   Karri, Ramesh ^a,b  

^a IEEE   (United States)

^b POLYTECHNIC UNIVERSITY   (United States)

Author keywords

Algorithm level recomputing; Concurrent error detection; Fault tolerance; High level synthesis; Register transfer level

Indexed keywords

ALGORITHM LEVEL COMPUTING; ALLOCATION DIVERSITY; CONCURRENT ERROR DETECTION; HIGH-LEVEL SYNTHESIS; OPERATION-TO-OPERATOR ALLOCATION; REGISTER TRANSFER LEVEL;

ADDERS; ALGORITHMS; COMPUTATIONAL METHODS; FAILURE ANALYSIS; FAULT TOLERANT COMPUTER SYSTEMS; LOGIC CIRCUITS; PROBABILITY; SHIFT REGISTERS;

ERROR DETECTION;

EID: 0036733232     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2002.801110     Document Type: Article

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