Instruction-based system-level power evaluation of system-on-a-chip peripheral cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 10, Issue 6, 2002, Pages 856-863

  Givargis, Tony ^a   Vahid, Frank ^b   Henkel, Jörg ^c  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of California Riverside   (United States)

^c NEC LABORATORIES AMERICA   (United States)

Author keywords

Low power design; Power estimation; System level simulation; System on a chip design

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; OBJECT ORIENTED PROGRAMMING;

POWER EVALUATIONS;

MICROPROCESSOR CHIPS;

EID: 0037004812     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2002.808443     Document Type: Review

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