Low-power system-level design of VLSI packet switching fabrics

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 6, 2001, Pages 723-738

  Wassal, Amr G ^a,b   Hasan, M A ^a,c  

^a IEEE   (Canada)

^b PMC Sierra Ltd Burnaby   (Canada)

^c UNIVERSITY OF WATERLOO   (Canada)

Author keywords

D BMAP model; Design framework; Integer nonlinear optimization; Low power; Packet switching fabrics; System level

Indexed keywords

DISCRETE TIME BATCH MARKOVIAN ARRIVAL PROCESS; INTEGER NONLINEAR OPTIMIZATION PROBLEM; LOW POWER SYSTEM LEVEL DESIGN; PACKET SWITCHING FABRICS; POWER OPTIMIZATION PROBLEM; STOCHASTIC TRAFFIC MODEL;

COMPUTER AIDED DESIGN; MARKOV PROCESSES; MATHEMATICAL MODELS; OPTIMIZATION; PERFORMANCE; TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

PACKET SWITCHING;

EID: 0035369394     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.924826     Document Type: Article

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