Software-based self-testing methodology for processor cores

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 369-380

  Chen, Li ^a,b   Dey, Sujit ^a,b  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

At speed testing; Instructions; Processors; Self test; Structural test

Indexed keywords

AT-SPEED TESTING; PROCESSOR CORES; STRUCTURAL TEST;

BUILT-IN SELF TEST; COMPUTER AIDED LOGIC DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; THEOREM PROVING;

INTEGRATED CIRCUIT TESTING;

EID: 0035272504     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913755     Document Type: Article

References (30)

1. Built-in self-test for digital integrated circuits
2. A distributed BIST control scheme for complex VLSI devices
3. Logic BIST for large industrial designs: Real issues and case studies
4. Mixed-mode BIST using embedded processors
5. Accumulator based deterministic BIST
6. Self test using unequiprobable random patterns
7. Built-in self-test with weighted random-pattern hardware
8. On the design of random-pattern testable PLA based on weighted random-pattern testing
9. Arithmetic built-in self-test for DSP cores
10. Optimal hardware pattern generation for functional BIST
11. Deterministic BIST with partial scan
12. DS-LFSR: A new BIST TPG for low-heat dissipation
13. Low power BIST by filtering nondetecting vectors
14. Testing the 400 MHz IBM generation-4 CMOS chip
15. Application of deterministic logic BIST on industrial circuits
16. Manufacturing pattern development for the alpha 21164 microprocessor
17. Testing a system-on-a-chip with embedded microprocessor
18. Native mode functional test generation for processors with applications to self test and design validation
19. Instruction randomization self test for processor cores
20. Built-in self-test for system-on-a-chip
21. A novel functional test generation method for processors using commercial ATPG
22. CHEETA: Composition of hierarchical sequential tests using ATKET
23. Test generation for gigahertz processors using an automatic functional constraint extractor
24. Test generation for ultra-large circuits using ATPG constraints and test-pattern templates
25. How seriously do you take possible-detect faults?