Low power BIST by filtering non-detecting vectors

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 16, Issue 3, 2000, Pages 193-202

  Manich, Salvador ^a   Gabarró, Albert ^a   Lopez, Marcos ^a   Figueras, Joan ^a   Girard, Patrick ^b   Guiller, Loïs ^b   Landrault, Christian ^b   Pravossoudovitch, Serge ^b   Teixeira, J Paulo ^c   Dos Santos, Marcelino Bicho ^c  

^a UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^b LIRMM   (France)

^c INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER SUPPLIES TO APPARATUS; SEQUENTIAL CIRCUITS; SHIFT REGISTERS;

BENCHMARK CIRCUITS; NONDETECTING VECTORS; POWER CONSUMPTION; PSEUDO RANDOM VECTORS; RESEEDING STRATEGY;

BUILT-IN SELF TEST;

EID: 0033689730     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008331029249     Document Type: Article

References (13)

1. W.H. Debany, "Quiescent Scan Design For Testing Digital Logic Circuits," Proc. Dual-Use Tech. & App., May 1994, pp. 142-151.
2. Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," VLSI Test Symp., April 1993, pp. 4-9.
3. R.M. Chou, K.K. Saluja, and V.D. Agrawal, "Power Constraint Scheduling of Tests," Proc. 7th International Conf. VLSI Des., Jan. 1994, pp. 271-274.
4. H. Cheung and S.K. Gupta, "A Bist Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation," Int. Test Conf., Oct. 1996, pp. 386-395.
5. S. Wang and S.K. Gupta, "DS-LFSR: A New BIST TPG for Low Heat Dissipation," Int. Test Conf., Oct. 1997, pp. 848-857.
6. Al Hertwig and H.-J. Wunderlich, "Low Power Serial Built-In Self-Test," Eur. Test Work, May 1998, pp. 49-53.
7. X. Zhang, K. Roy, and S. Bawmik, "POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing," Proc. 12th International Conf. VLSI Design, Jan. 1999, pp. 416-422.
8. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, "A Test Vector Inhibiting Technique for Low Energy BIST Design," VLSI Test Sym., April 1999, pp. 407-412.
9. S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Register," Proc. Int. Test Conf., Oct. 1992, pp. 120-129.
10. P. Girard, L. Guiller, J. Figueras, S. Manich, P. Teixeira, and M. Santos, "Low Power Pseudo-random BIST: On Selecting the LFSR Seed," Dis. Cir. Int. Sist., Nov. 1998, pp. 166-172.
11. W. Nebel and J. Mermet, "Low Power Design in Deep Submicron Electronics," NATO ASI Series, Vol. 337, Kluwer, 1996.
12. S. Manich and J. Figueras, "Sensitivity of the Worst Case Dynamic Power Estimation on Delay and Filtering Models," Pow. Tim. Mod. Opt. Sim., Sept. 1997, pp. 141-150.
13. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, and A.S.-Vincentelli, "SIS: A System for Sequential Circuit Synthesis," Elec. Res. Lab. Memo. UCB/ERL M92/41, May 1992.