Arithmetic built-in self-test for DSP cores

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 11, 1997, Pages 1358-1369

  Radecka, Katarzyna ^a,b   Rajski, Janusz ^a,b   Tyszer, Jerzy ^a,b  

^a NOKIA RESEARCH CENTER   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

Accumulator based compaction; Arithmetic generators; Built in self test; Data path architectures; Dsp cores; Multiple scan design; State coverage; Two dimensional generators

Indexed keywords

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; TESTING;

BUILT-IN SELF-TEST; TWO-DIMENSIONAL GENERATORS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0031276326     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.663825     Document Type: Article

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