Optimal hardware pattern generation for functional BIST

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 292-297

  Cataldo, Silvia ^a   Chiusano, Silvia ^a   Prinetto, Paolo ^a   Wunderlich, Hans Joachim ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF STUTTGART   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DETECTION CAPABILITY; DETERMINISTIC TEST PATTERN; DIGITAL SYSTEM; HARDWARE TEST; LINEAR FEEDBACK SHIFT REGISTERS; PATTERN GENERATION; PATTERN GENERATOR; PERFORMANCE DEGRADATION;

EXHIBITIONS; FAULT DETECTION; OPTIMIZATION; SHIFT REGISTERS;

HARDWARE;

EID: 3142671162     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840286     Document Type: Conference Paper

References (15)

1. S. Venkataraman, J. Rajski, S. Hellebrand, S. Tarnick, An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Register, IEEE International Conference on Computer-Aided Design, 1993, pp. 572-577
2. H. J Wunderlich, G. Kiefer, Bit-flipping BIST, IEEE International Conference on Computer-Aided Design, 1996, pp. 337-343
3. S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda, Cellular Automata for Deterministic Sequential Test Pattern Generation, IEEE VLSI Test Symposium, 1997, pp. 60-65
4. M. Abramovici, M. A. Breuer, A. D. Friedman, Digital System Testing and Testable Design, Computer Science Press, 1990
5. S. Gupta, J. Rajski, J. Tyszer, Arithmetic Adaptive Generators of Pseudo-Exhaustive Test Patterns, IEEE Transactions on Computers, vol. 8, num. 45, 939-949, August, 1996
6. J. Rajski, J. Tyszer, Multiplicative Window Generators of Pseudo Random Test Vectors, IEEE European Design & Test Conference, 1996, pp. 42-48
7. A. P. Stroele, F. Mayer, Methods to reduce Test Application Time for Accumulator-Based Self -Test, IEEE VLSI Test Symposium, 1997, pp. 48-53
8. A. P. Stroele, Arithmetic Pattern Generation for Built-In Self Test, IEEE International Conference Computer Design, 1996, pp. 131-134
9. J. Rajski, J. Tyszer, Arithmetic Built-In Self-Test for Embedded Systems, Prentice Hall, 1998
10. S. Gupta, J. Rajski, J. Tyszer, Test Pattern Generation Based on Arithmetic Operations, IEEE International Conference on Computer-Aided Design, 1994, pp. 117-122
11. R. Dorsch, H. -J. Wunderlich, Accumulator Based Deterministic BIST, IEEE International Test Conference, 1998, pp. 412-421
12. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Addison-Wesley, 1989
13. F. Brglez and H. Fujiwara, A Neutral Netlist of 10 Combinatorial Benchmark Circuits, IEEE International Symposium on Circuits and Systems, 1985
14. F. Brglez, D. Bryan, K. Kozminski, Combinatorial Profiles of Sequential Benchmark Circuits, IEEE International Symposium on Circuits and Systems, 1989, pp. 1129-1234
15. Sunrise Reference Manual, Sunrise Test Systems, 1995