-
6
-
-
0022219373
-
-
1985, pp. 212-222.
-
N. Khurana, T. Maloney, and W. Yeh ESD on CHMOS devices-equivalent circuits, physical models and failure mechanisms, in Proc. IEEE Int. Reliability Physics Symp., 1985, pp. 212-222.
-
ESD on CHMOS Devices-equivalent Circuits, Physical Models and Failure Mechanisms, in Proc. IEEE Int. Reliability Physics Symp.
-
-
Khurana, N.1
Maloney, T.2
Yeh, W.3
-
12
-
-
0033279078
-
-
1999, pp. 212-224.
-
S. Voldman, W. Anderson, R. Ashton, M. Chaîne, C. Duvvury, T. Maloney, and E. A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies, in EOS/ESD Symp. Proc., 1999, pp. 212-224.
-
A Strategy for Characterization and Evaluation of ESD Robustness of CMOS Semiconductor Technologies, in EOS/ESD Symp. Proc.
-
-
Voldman, S.1
Anderson, W.2
Ashton, R.3
Chaîne, M.4
Duvvury, C.5
Maloney, T.6
-
16
-
-
0032183002
-
-
vol. 21, pp. 278-285, Oct. 1998.
-
_ Very fast transmission-line pulsing of integrated structures and the charged device model, IEEE Trans. Comp., Packag., Manufact. Technoi, vol. 21, pp. 278-285, Oct. 1998.
-
Very Fast Transmission-line Pulsing of Integrated Structures and the Charged Device Model, IEEE Trans. Comp., Packag., Manufact. Technoi
-
-
-
17
-
-
0033279806
-
-
1999, pp. 28-37.
-
H. Wolf, H. Gieser, and W. Wilkening Analyzing the switching behavior of ESD protection transistors by very fast transmission-line pulsing, in EOS/ESD Symp. Proc., 1999, pp. 28-37.
-
Analyzing the Switching Behavior of ESD Protection Transistors by Very Fast Transmission-line Pulsing, in EOS/ESD Symp. Proc.
-
-
Wolf, H.1
Gieser, H.2
Wilkening, W.3
-
19
-
-
33747935976
-
-
2000, pp. 214-217.
-
S. Voldman, P. Juliano, N. Schmidt, A. Botula, R. Johnson, L. Lanzerotti, N. Feilchenfeld, A. Joseph, J. Malinowski, E. Eld, V Gross, C. Brennan, J. Dunn, D. Harame, D. Herman, and B. Meyerson ESD robustness of a BiCMOS SiGe technology, in Bipolar/BiCMOS Circuits and Technology Meeting, 2000, pp. 214-217.
-
ESD Robustness of a BiCMOS SiGe Technology, in Bipolar/BiCMOS Circuits and Technology Meeting
-
-
Voldman, S.1
Juliano, P.2
Schmidt, N.3
Botula, A.4
Johnson, R.5
Lanzerotti, L.6
Feilchenfeld, N.7
Joseph, A.8
Malinowski, J.9
Eld, E.10
Gross, V.11
Brennan, C.12
Dunn, J.13
Harame, D.14
Herman, D.15
Meyerson, B.16
-
20
-
-
0031701486
-
-
1998, pp. 293-301.
-
S. Voldman, R. Gauthier, D. Reinhart, and K. Morriseau High-current transmission-line pulse characterization of aluminum and copper interconnects for advanced CMOS semiconductor technologies, in Int. Reliability Physics Symp., 1998, pp. 293-301.
-
High-current Transmission-line Pulse Characterization of Aluminum and Copper Interconnects for Advanced CMOS Semiconductor Technologies, in Int. Reliability Physics Symp.
-
-
Voldman, S.1
Gauthier, R.2
Reinhart, D.3
Morriseau, K.4
-
21
-
-
0030386832
-
-
1996, pp. 291-301.
-
S. Voldman, R. Schulz, J. Howard, V Gross, S. Wu, A. Yapsir, D. Sadana, H. Hovel, J. Walker, F. Assaderaghi, B. Chen, J. Y.-C. Sun, and G. Shahidi CMOS-on-SOI ESD protection networks, in EOS/ESD Symp. Proc., 1996, pp. 291-301.
-
CMOS-on-SOI ESD Protection Networks, in EOS/ESD Symp. Proc.
-
-
Voldman, S.1
Schulz, R.2
Howard, J.3
Gross, V.4
Wu, S.5
Yapsir, A.6
Sadana, D.7
Hovel, H.8
Walker, J.9
Assaderaghi, F.10
Chen, B.11
Sun Y-C, J.12
Shahidi, G.13
-
23
-
-
0028744520
-
-
1994, pp. 141-149.
-
S. Dabral, R. Aslett, and T. Maloney Core clamps for low voltage technologies, in EOS/ESD Symp. Proc., 1994, pp. 141-149.
-
Core Clamps for Low Voltage Technologies, in EOS/ESD Symp. Proc.
-
-
Dabral, S.1
Aslett, R.2
Maloney, T.3
-
24
-
-
33748000923
-
-
1992, pp. 258-264.
-
M.-D. Ker, C.-Y Wu, and C.-Y Lee A novel CMOS ESD/EOS protection circuit with full-SCR structures, in EOS/ESD Symp. Proc., 1992, pp. 258-264.
-
A Novel CMOS ESD/EOS Protection Circuit with Full-SCR Structures, in EOS/ESD Symp. Proc.
-
-
Ker, M.-D.1
Wu, C.-Y.2
Lee, C.-Y.3
-
25
-
-
33747928583
-
-
2000, pp. 162-170.
-
Y Warig, P. Juliano, S. Joshi, and E. Rosenbaum Electrothermal modeling of ESD diodes in bulk-Si and SOI technologies, in EOS/ESD Symp. Proc., 2000, pp. 162-170.
-
Electrothermal Modeling of ESD Diodes in Bulk-Si and SOI Technologies, in EOS/ESD Symp. Proc.
-
-
Warig, Y.1
Juliano, P.2
Joshi, S.3
Rosenbaum, E.4
-
26
-
-
0028734222
-
-
1994, pp. 266-272.
-
J. R. M. Luchies, C. G. C. M. de Kort, and J. F. Verwiej Fast turn-on of an nMOS ESD protection transistor: Measurements and simulation, in EOS/ESD Symp. Proc., 1994, pp. 266-272.
-
Fast Turn-on of an NMOS ESD Protection Transistor: Measurements and Simulation, in EOS/ESD Symp. Proc.
-
-
Luchies, J.R.M.1
De Kort, C.G.C.M.2
Verwiej, J.F.3
-
27
-
-
0030274006
-
-
vol. 36, no. 11/12, pp. 1739-1742, 1996.
-
C. RUSS, K. Verhaege, K. Bock, G. Groeseneken, and H. Maes Simulation study for the COM ESD behavior of the grounded-gate nMOS, Microelectron. Reliability, vol. 36, no. 11/12, pp. 1739-1742, 1996.
-
Simulation Study for the COM ESD Behavior of the Grounded-gate NMOS, Microelectron. Reliability
-
-
Russ, C.1
Verhaege, K.2
Bock, K.3
Groeseneken, G.4
Maes, H.5
-
28
-
-
0030384441
-
-
1996, pp. 302-315.
-
C. RUSS, K. Verhaege, K. Bock, P. Roussel, G. Groeseneken, and H. Maes A compact model for the grounded-gate nMOS behavior under COM ESD stress, in EOS/ESD Symp. Proc., 1996, pp. 302-315.
-
A Compact Model for the Grounded-gate NMOS Behavior under COM ESD Stress, in EOS/ESD Symp. Proc.
-
-
Russ, C.1
Verhaege, K.2
Bock, K.3
Roussel, P.4
Groeseneken, G.5
Maes, H.6
-
29
-
-
0030273998
-
-
vol. 36, no. 11/12, pp. 1735-1738, 1996.
-
G. Meneghesso, J. R. M. Luchies, F. G. Kuper, and A. J. Mouthaan Turn-on speed of grounded gate nMOS ESD protection transistors, Microelectron. Reliability, vol. 36, no. 11/12, pp. 1735-1738, 1996.
-
Turn-on Speed of Grounded Gate NMOS ESD Protection Transistors, Microelectron. Reliability
-
-
Meneghesso, G.1
Luchies, J.R.M.2
Kuper, F.G.3
Mouthaan, A.J.4
-
32
-
-
0034538958
-
-
2000, pp. 287-295.
-
J. Wu, P. Juliano, and E. Rosenbaum Breakdown and latent damage of ultrathin gate oxides under ESD stress conditions, in EOS/ESD Symp. Proc., 2000, pp. 287-295.
-
Breakdown and Latent Damage of Ultrathin Gate Oxides under ESD Stress Conditions, in EOS/ESD Symp. Proc.
-
-
Wu, J.1
Juliano, P.2
Rosenbaum, E.3
-
35
-
-
0032272374
-
-
1998, pp. 97-100.
-
J. Rodriguez, M. C. Smayling, and W. L. Wilson ESD circuit synthesis and analysis using TCAD and SPICE, in Proc. IEDM, 1998, pp. 97-100.
-
ESD Circuit Synthesis and Analysis Using TCAD and SPICE, in Proc. IEDM
-
-
Rodriguez, J.1
Smayling, M.C.2
Wilson, W.L.3
-
36
-
-
0031249221
-
-
vol. 37, no. 10/11, pp. 1457-1460, 1997.
-
G. Notermans, F. Kuper, and J.-M. Luchies Using an SCR as ESD protection without latch-up danger, Microelectron. Reliability, vol. 37, no. 10/11, pp. 1457-1460, 1997.
-
Using an SCR as ESD Protection without Latch-up Danger, Microelectron. Reliability
-
-
Notermans, G.1
Kuper, F.2
Luchies, J.-M.3
-
37
-
-
0030836964
-
-
vol. 32, pp. 38-51, Jan. 1997.
-
M.-D. Ker, H.-H. Chang, and C.-Y. Wu A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs, IEEE J. Solid-State Circuits, vol. 32, pp. 38-51, Jan. 1997.
-
A Gate-coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-submicron Low-voltage CMOS ICs, IEEE J. Solid-State Circuits
-
-
Ker, M.-D.1
Chang, H.-H.2
Wu, C.-Y.3
-
38
-
-
33748022003
-
-
1992, pp. 234-242.
-
B. G. Carbajal, III, R. A. Cline, and B. H. Andresen A successful HBM ESD protection circuit for micron and submicron level CMOS, in EOS/ESD Symp. Proc., 1992, pp. 234-242.
-
A Successful HBM ESD Protection Circuit for Micron and Submicron Level CMOS, in EOS/ESD Symp. Proc.
-
-
Carbajal III, B.G.1
Cline, R.A.2
Andresen, B.H.3
-
40
-
-
33747989786
-
-
D. B. Eistreich The physics and modeling of latch-up in CMOS integrated circuits, Ph.D. dissertation, Stanford Univ., Stanford, CA, 1981.
-
The Physics and Modeling of Latch-up in CMOS Integrated Circuits, Ph.D. Dissertation, Stanford Univ., Stanford, CA, 1981.
-
-
Eistreich, D.B.1
-
41
-
-
0020091286
-
-
29, p. 254, 1982.
-
B. Eitan and D. Frohman-Bentchkowsky Surface conduction in shortchannel MOS devices as a limitation to VLSI scaling, IEEE Trans. Electron Devices, vol. ED-29, p. 254, 1982.
-
Surface Conduction in Shortchannel MOS Devices as a Limitation to VLSI Scaling, IEEE Trans. Electron Devices, Vol. ED
-
-
Eitan, B.1
Frohman-Bentchkowsky, D.2
-
42
-
-
0024176693
-
-
1988, pp. 201-205.
-
R. N. Rountree, C. Duvvury, T. Maki, and H. Stiegler A process-tolerant input protection circuit for advanced CMOS processes, in EOS/ESD Symp. Proc., 1988, pp. 201-205.
-
A Process-tolerant Input Protection Circuit for Advanced CMOS Processes, in EOS/ESD Symp. Proc.
-
-
Rountree, R.N.1
Duvvury, C.2
Maki, T.3
Stiegler, H.4
-
44
-
-
33747904622
-
-
private communication.
-
R. Ashton, private communication.
-
-
-
Ashton, R.1
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