Using an SCR as ESD protection without latch-up danger

Microelectronics Reliability

Volumn 37, Issue 10-11, 1997, Pages 1457-1460

  Notermans, Guido ^a   Kuper, Fred ^a   Luchies, Jan Marc ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC DISCHARGES; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DEVICE TESTING;

ANODE TO CATHODE SPACING; SEMICONDUCTOR CONTROLLED RECTIFIERS;

ELECTRIC RECTIFIERS;

EID: 0031249221     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(97)00086-3     Document Type: Article

References (6)

1. L. Avery, "Using SCRs as transient protection structures in integrated circuits", EOS/ESD Symposium Proceedings (1984) 177.
2. A. Chatterjee and T. Polgreen, "A low voltage triggering SCR for on-chip ESD protection at output and input pads", IEEE Elec. Dev. Lett. EDL-12 (1991) 21.
3. J. Seitchik A. Chatterjee and Ping Yang, "An analytical model of holding voltage for latch-up in epitaxial CMOS", IEEE Elec. Dev. Lett. EDL-8 (1987) 157.
4. A. Chatterjee, J. Seitchik, J.-H. Chern, Ping Yang and C.-C. Wei, "Direct evidence supporting the premises of a two-dimensional diode model for the parasitic thyristor in CMOS circuits built on thin epi", IEEE Elec. Dev. Lett. EDL-9 (1988) 509.
5. T. Maloney and N. Khurana, "Transmission line pulsing techniques for circuit modeling of ESD phenomena", EOS/ESD Symposium Proceedings (1985) 49.
6. F. Kuper, J. Bruines and J.-M. Luchies, "Suppression of soft failures in a submicron CMOS process", EOS/ESD Symposium proceedings (1993) 117.