Simulation study for the CDM ESD behaviour of the grounded-gate NMOS

Microelectronics Reliability

Volumn 36, Issue 11-12 SPEC. ISS., 1996, Pages 1739-1742

  Russ, C ^a   Verhaege, K ^a,b   Bock, K ^a   Groeseneken, G ^a   Maes, H E ^a  

^a IMEC   (Belgium)

^b SARNOFF CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CIRCUIT OSCILLATIONS; DIFFUSION IN SOLIDS; ELECTRIC CHARGE; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS; THERMAL STRESS; ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC GROUNDING; ELECTROSTATICS; MOSFET DEVICES; STRESSES;

COMPACT TRANSISTOR MODEL; ELECTRIC STRESS; CHARGED DEVICE MODEL (CDM); ELECTROSTATIC DISCHARGES;

MOS DEVICES; BIPOLAR TRANSISTORS;

EID: 0030274006     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(96)00187-4     Document Type: Article

References (8)

1. C. Duvvury, How Fast Does a Protection Device Turn On?, Threshold - ESD Association Newsletter, December, pp. 1, 9, (1995).
2. C.H. Diaz, et al., Circuit-Level Electrothermal Simulation of Electrical Overstress Failures in Advanced MOS I/O Protection Devices, IEEE Trans. on CAD of ICs and Circuits, Vol. 13, No. 4, pp. 482-493, (1994).
3. C. Russ, et al., Compact Electro-Thermal Simulation of BSD-Protection Elements, Quality and Reliability Engineering International, Vol. 10, pp. 335-340, (1994).
4. A. Amerasekera, et al., Modelling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations, Proc. IRPS, pp. 318-326, (1996).
5. C. Russ, et al., A Compact Model for the Grounded-Gate nMOS Behaviour under CDM ESD Stress, Proc. EOS/ESD, (1996).
6. G. Krieger, The Dynamics of Electrostatic Discharge Prior to Bipolar Action Related Snapback, Proc. EOS/ESD, pp. 136-144, (1989).
7. A. Amerasekera, et al. Characterisation and Modelling of Second Breakdown in nMOSt's for the Extraction of ESD-Related Process and Design Parameters, IEEE TED, Vol. 38, pp. 2161-2168, (1991).
8. K. Verhaege, et al., nMOS Transistor Behaviour under CDM Stress Conditions and Relation to Other ESD Models, Proc. ESREF, pp. 117-124, (1995).