SCOPUS 정보 검색 플랫폼

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1990, Pages 75-76

A low-voltage triggering SCR for on-chip ESD protection at output and input pads

(2) Chatterjee, Amitava a Polgreen, Thomas a

a TEXAS INSTRUMENTS (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE THRESHOLDS; GATE LENGTH; LOW-VOLTAGE; NMOS TRANSISTORS; ON-CHIP ESD PROTECTION; ON-CHIP PROTECTION; OUTPUT BUFFER; PROTECTION CIRCUITS; TRIGGER VOLTAGE; TUNABILITIES;

ELECTROSTATIC DISCHARGE; ELECTRIC SWITCHES, SEMICONDUCTOR; ELECTROSTATICS--ELECTRIC CHARGE; TRANSISTORS, FIELD EFFECT;

ELECTROSTATIC DEVICES; SEMICONDUCTOR DEVICES, MOS;

DIGEST OF PAPERS; ESD PROTECTION; NMOS TRANSISTORS; SCR;

EID: 0025659612 PISSN: 07431562 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/VLSIT.1990.111015 Document Type: Conference Paper

Times cited : (18)

References (9)

1
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- 1989 EOS/ESD Symposium Proceedings , vol.EOS-11
- Polgreen, T.¹ Chatterjee, A.²

2
- 0021629272
- Using SCRs as transient protection structures in integrated circuits
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- 1984 EOS/ESD Symposium Proceedings , vol.EOS-5 , pp. 177
- Avery, L.R.¹

3
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- 1988 EOS/ESD Symposium Proceedings , vol.EOS-10 , pp. 201
- Rountree, R.¹ Duvvury, C.² Maki, T.³ Stiegler, H.⁴

4
- 0343635497
- Novel ESD protection for advanced CMOS output drivers
- G. Rieck and R. Manely, "Novel ESD protection for advanced CMOS output drivers," 1989 EOS/ESD Symposium Proceedings, EOS-11.
- 1989 EOS/ESD Symposium Proceedings , vol.EOS-11
- Rieck, G.¹ Manely, R.²

5
- 0023603922
- An 0.8 μm CMOS technology for high performance logic applications
- R.A. Chapman, et al., "An 0.8 μm CMOS technology for high performance logic applications," 1987 IEDM Technical Digest, p. 362.
- 1987 IEDM Technical Digest , pp. 362
- Chapman, R.A.¹

6
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- John Wiley, New York
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- (1977) Semiconductor Power Devices
- Ghandhi, S.K.¹

7
- 0021389354
- Surface induced latchup in VLSI CMOS circuits
- D. Takacs, C. Werner, J. Harter and U. Schwabe, "Surface induced latchup in VLSI CMOS circuits," IEEE Trans. on Electron Dev., ED-31, p. 279, 1984.
- (1984) IEEE Trans. on Electron Dev. , vol.ED-31 , pp. 279
- Takacs, D.¹ Werner, C.² Harter, J.³ Schwabe, U.⁴

8
- 0020091286
- Surface conduction in short-channel MOS devices as a limitation to VLSI scaling
- B. Eitan and D. Frohman-Bentchkowsky, "Surface conduction in short-channel MOS devices as a limitation to VLSI scaling," /it IEEE Trans. Electron Dev., ED-29, p. 254, 1982.
- (1982) It IEEE Trans. Electron Dev. , vol.ED-29 , pp. 254
- Eitan, B.¹ Frohman-Bentchkowsky, D.²

9
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- Input protection design for overall chip reliability
- C. Duvvury et al., "Input protection design for overall chip reliability," 1989 EOS/ESD Symposium Proceedings, EOS-11.
- 1989 EOS/ESD Symposium Proceedings , vol.EOS-11
- Duvvury, C.¹

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