Strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1999, Pages 212-224

  Voldman, S ^a   Anderson, W ^a   Ashton, R ^a   Chaine, M ^a   Duvvury, C ^a   Maloney, T ^a   Worley, E ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; ELECTRIC DISCHARGES; ELECTROSTATICS; INTEGRATED CIRCUIT TESTING; SEMICONDUCTOR DEVICE MANUFACTURE;

ELECTROSTATIC DISCHARGES (ESD);

CMOS INTEGRATED CIRCUITS;

EID: 0033279078     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)