Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 3, 2003, Pages 457-463

  Huang, Xuejue ^a   Restle, Phillip ^b   Bucelot, Thomas ^b   Cao, Yu ^c   King, Tsu Jae ^c   Hu, Chenming ^c  

^a RAMBUS INC   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Clock distribution; Inductance; Proximity effects; Timing analysis

Indexed keywords

COMPUTER SIMULATION; ELECTRIC RESISTANCE; INDUCTANCE; MATHEMATICAL MODELS; OPTIMIZATION; TIMING CIRCUITS;

CLOCK DISTRIBUTION; ELECTROMAGNETIC SIMULATION; MULTIGIGAHERTZ CLOCK NETWORK DESIGN; PROXIMITY EFFECTS; TIMING ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037347427     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.808313     Document Type: Article

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