Exploiting the on-chip inductance in high-speed clock distribution networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 963-973

  Ismail, Yehea I ^a,b   Friedman, Eby G ^c   Neves, Jose L ^d  

^a IEEE   (United States)

^b Northwestern University   (United States)

^c University of Rochester   (United States)

^d IBM MICROELECTRONICS   (United States)

Author keywords

Clock distribution; CMOS; Inductance; Power; RLC

Indexed keywords

CLOCK DISTRIBUTION NETWORKS;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INDUCTANCE; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS;

TIMING CIRCUITS;

EID: 0035704577     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974910     Document Type: Article

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