Performance optimization by wire and buffer sizing under the transmission line model

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 192-198

  Chen, Tai Chen ^a   Pan, Song Ra ^b   Chang, Yao Wen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ERROR ANALYSIS; GATES (TRANSISTOR); INTERCONNECTION NETWORKS; OPTIMIZATION; TRANSMISSION LINE THEORY;

DELAY COMPUTATIONS;

BUFFER STORAGE;

EID: 0035183802     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955024     Document Type: Article

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