Vertical Delay Modeling of Copper/Carbon Nanotube Composites in a Tapered through Silicon Via

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2017, Pages 80-85

  Rao, Madhav ^a  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

Author keywords

CNTs; Delay; Interconnects; TSV

Indexed keywords

CARBON; CARBON NANOTUBES; COPPER; DELAY CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUIT MANUFACTURE; NANOTUBES; NETWORK COMPONENTS; OPTICAL INTERCONNECTS; YARN;

3-D INTEGRATED CIRCUIT DESIGNS; CHIP FUNCTIONALITY; CNTS; CYLINDRICAL SHAPES; DELAY; NANOTUBE COMPOSITES; THROUGH-SILICON-VIA; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 85028062885     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2017.19     Document Type: Conference Paper

References (32)

1. J. Mao, "Applications of carbon nanotube technology for nextgeneration high speed and microwave circuits, " in Microwave Technology and Computational Electromagnetics, 2009. ICMTCE. International Conference on, Nov 2009, pp. 7-7.
2. Y. Awano, S. Sato, M. Nihei, T. Sakai, Y. Ohno, and T. Mizutani, "Carbon nanotubes for vlsi: Interconnect and transistor applications, " Proceedings of the IEEE, vol. 98, no. 12, pp. 2015-2031, Dec 2010.
3. N. Alam, A. Kureshi, M. Hasan, and T. Arslan, "Carbon nanotube interconnects for low-power high-speed applications, " in Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, May 2009, pp. 2273-2276.
4. P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, B. Michel, and H. Reichi, "Through silicon via processes and reliability for wafer-level 3d system integration, " in Proc. Elec. Comp. Tech. Conf, 2008, pp. 841-846.
5. Y. Chai, P. C. Chan, Y. Fu, Y. Chuang, and C. Liu, "Copper/carbon nanotube composite interconnect for enhanced electromigration resistance, " in Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, May 2008, pp. 412-420.
6. B. Kim, C. Sharbono, T. Ritzdorf, and D. Schmauch, "Factors affecting copper filling process within high aspect ratio deep vias for 3d chip stacking, " in Electronic Components and Technology Conference, 2006. Proceedings. 56th, 2006, pp. 6 pp.-.
7. C. C. Yang, F. Baumann, P. C. Wang, S. Lee, P. Ma, J. AuBuchon, and D. Edelstein, "Characterization of copper electromigration dependence on selective chemical vapor deposited cobalt capping layer thickness, " IEEE Electron Device Letters, vol. 32, no. 4, pp. 560-562, April 2011.
8. Y. Li, K. Croes, T. Kirimura, Y. K. Siew, and Z. Tkei, "Copper electromigration failure times evaluated over a wide range of voiding phases, " in Reliability Physics Symposium (IRPS), 2012 IEEE International, April 2012, pp. EM. 1. 1-EM. 1. 4.
9. F. Su, X. Pan, P. Huang, Y. Guan, J. Chen, and S. Ma, "Influence of copper pumping on integrity and stress of through-silicon vias, " IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 8, pp. 1221-1225, Aug 2016.
10. U. Ghoshal and L. N. Smith, "Finite element analysis of skin effect in copper interconnects at 77 k and 300 k, " in Microwave Symposium Digest, 1988., IEEE MTT-S International, May 1988, pp. 773-776 vol. 2.
11. C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact ac modeling and performance analysis of through-silicon vias in 3-d ics, " IEEE Transactions on Electron Devices, vol. 57, no. 12, pp. 3405-3417, Dec 2010.
12. M. B. Jordan, Y. Feng, and S. L. Burkett, "Development of seed layer for electrodeposition of copper on carbon nanotube bundles, " Journal of Vacuum Science & Technology B, vol. 33, no. 2, 2015.
13. Y. Feng, G. E. McGuire, O. A. Shenderova, H. Ke, and S. L. Burkett, "Fabrication of copper/carbon nanotube composite thin films by periodic pulse reverse electroplating using nanodiamond as a dispersing agent, " Thin Solid Films, vol. 615, pp. 116-121, 2016.
14. Y. Feng and S. L. Burkett, "Modeling a coppe/carbon nanotube composite for applications in electronic packaging, " Computational Materials Science, vol. 97, pp. 1-5, 2015.
15. S. Sakurai, M. Inaguma, D. N. Futaba, M. Yumura, and K. Hata, "Diameter and density control of single-walled carbon nanotube forests by modulating ostwald ripening through decoupling the catalyst formation and growth processes, " Small, vol. 9, no. 21, pp. 3584-3592, 2013.
16. Y. Feng and S. Burkett, "Fabrication and electrical performance of through silicon via interconnects filled with a copper/carbon nanotube composite, " Journal of Vacuum Science & Technology B, vol. 33, no. 2, 2015.
17. N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Addison Wesley, 2010, vol. 1, pp. 181-200.
18. A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny, "Unified logical effort; a method for delay evaluation and minimization in logic paths with rc interconnect, " IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 5, pp. 689-696, May 2010.
19. N. Niioka, M. Watanabe, R. Karel, T. Kobayashi, M. Imai, M. a. Fukase, and A. Kurokawa, "Impact of on-chip interconnects on vertical signal propagation in 3d ics, " in 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Nov 2014, pp. 607-610.
20. I. U. Abhulimen, S. Polamreddy, S. Burkett, L. Cai, and L. Schaper, "Effect of process parameters on via formation in si using deep reactive ion etching, " Journal of Vacuum Science & Technology B, vol. 25, no. 6, pp. 1762-1770, 2007.
21. X. Chen, J. Tang, G. Xu, and L. Luo, "Development of deep reactive ion etching and cu electroplating of tapered via for 3d integration, " in Electronic Packaging Technology and High Density Packaging (ICEPTHDP), 2011 12th International Conference on, Aug 2011, pp. 1-3.
22. A. Naeemi, G. Huang, and J. D. Meindl, "Performance modeling for carbon nanotube interconnects in on-chip power distribution, " in 2007 Proceedings 57th Electronic Components and Technology Conference, May 2007, pp. 420-428.
23. A. Todri, S. Kundu, P. Girard, A. Bosio, L. Dilillo, and A. Virazel, "A study of tapered 3-d tsvs for power and thermal integrity, " Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, no. 2, pp. 306-319, Feb 2013.
24. M. Rao, "Electrical modeling of copper/carbon nanotubes for 3d integration, " in 2016 IEEE Nanotechnology, August 2016.
25. G. Miano, C. Forestiere, A. Maffucci, S. Maksimenko, and G. Slepyan, "Signal propagation in carbon nanotubes of arbitrary chirality, " Nanotechnology, IEEE Transactions on, vol. 10, no. 1, pp. 135-149, 2011.
26. C. Forestiere, A. Maffucci, and G. Miano, "On the evaluation of the number of conducting channels in multiwall carbon nanotubes, " IEEE Transactions on Nanotechnology, vol. 10, no. 6, pp. 1221-1223, Nov 2011.
27. A. Chiariello, A. Maffucci, and G. Miano, "Electrical behaviour of carbon nanotube through-silicon vias, " in Signal Propagation on Interconnects (SPI), 2011 15th IEEE Workshop on, May 2011, pp. 75-78.
28. J. Su, F. Wang, and W. Zhang, "Capacitance expressions and electrical characterization of tapered through-silicon vias for 3-d ics, " Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 5, no. 10, pp. 1488-1496, 2015.
29. M. Rao, "Electrical modeling and characterization of copper/carbon nanotubes in a tapered through silicon via, " in 30th international conference on vlsi design & 16th International Conference on Embedded Systems, January 2017.
30. C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact ac modeling and analysis of cu, w, and cnt based through-silicon vias (tsvs) in 3-d ics, " in Electron Devices Meeting (IEDM), 2009 IEEE International, Dec 2009, pp. 1-4.
31. G. Katti, M. Stucchi, K. de Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ics, " Electron Devices, IEEE Transactions on, vol. 57, no. 1, pp. 256-262, Jan 2010.
32. L. Tiantao and A. Srivastava, "Detailed electrical and reliability study of tapered tsvs, " in 3D Systems Integration Conference (3DIC), 2013 IEEE International, Oct 2013, pp. 1-7.