Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 838-843

  Kim, Bioh ^a   Sharbono, Charles ^a   Ritzdorf, Tom ^a   Schmauch, Dan ^a  

^a Semitool Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; COPPER; COST EFFECTIVENESS; ELECTRIC DELAY LINES; ELECTRODES; OPTIMIZATION; WAVEFORM ANALYSIS; WSI CIRCUITS;

ANGLE CONTROL; COPPER ELECTRODES; COPPER FILLING PROCESS; THROUGH-SILICON-VIA (TSV);

ELECTRONICS PACKAGING;

EID: 33845598283     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645755     Document Type: Conference Paper

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