Unified logical effort - A method for delay evaluation and minimization in logic paths with RC interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 5, 2010, Pages 689-696

  Morgenshtein, Arkadiy ^a,b   Friedman, Eby G ^c   Ginosar, Ran ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b INTEL CORPORATION   (Israel)

^c University of Rochester   (United States)

Author keywords

Delay minimization; Interconnect; Logical effort (LE); Power

Indexed keywords

CMOS LOGIC GATES; DELAY COMPONENT; DELAY MINIMIZATION; DELAY MODELS; GATE INPUT; GATE SIZING; LOGIC PATH; LOGICAL EFFORT; OUTPUT RESISTANCE; REPEATER INSERTION; TAPERED GATES; TIMING OPTIMIZATION; WIRE LENGTH;

ELECTRIC RESISTANCE; WIRE;

OPTIMIZATION;

EID: 77951877332     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2014239     Document Type: Article

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