Influence of Copper Pumping on Integrity and Stress of Through-Silicon Vias

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 6, Issue 8, 2016, Pages 1221-1225

  Su, Fei ^a   Pan, Xiaoxu ^a   Huang, Pengfei ^a   Guan, Yong ^b   Chen, Jing ^b   Ma, Shenglin ^c  

^a BEIHANG UNIVERSITY   (China)

^b PEKING UNIVERSITY   (China)

^c XIAMEN UNIVERSITY   (China)

Author keywords

Copper pumping; in situ experimental technique; infrared photoelasticity; integrity; scanning electron microscopy (SEM); stress; through silicon vias (TSVs)

Indexed keywords

COPPER; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; PUMPS; THERMAL STRESS;

EXPERIMENTAL TECHNIQUES; HIGH TEMPERATURE; MULTIPLE CYCLES; REAL TIME MEASUREMENTS; STRESS-FREE STATE; THERMAL LOADINGS; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84978919942     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2016.2583508     Document Type: Article

References (20)

1. J. U. Knickerbocker et al., "3-D silicon integration and silicon packaging technology using silicon through-vias," IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, Aug. 2006.
2. L. W. Schaper, S. L. Burkett, S. Spiesshoefer, G. V. Vangara, Z. Rahman, and S. Polamreddy, "Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 356-366, Aug. 2005.
3. Y. K. Tsui and S. W. R. Lee, "Design and fabrication of a flip-chipon-chip 3-D packaging structure with a through-silicon via for underfill dispensing," IEEE Trans. Adv. Packag., vol. 28, no. 3, pp. 413-420, Aug. 2005.
4. P. Kumar, I. Dutta, and M. S. Bakir, "Interfacial effects during thermal cycling of Cu-filled through-silicon vias (TSV)," J. Electron. Mater., vol. 41, no. 2, pp. 322-335, Feb. 2012.
5. D. Malta et al., "Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs," in Proc. IEEE 61st Electron. Compon. Technol. Conf., Lake Buena Vista, FL, USA, May/Jun. 2011, pp. 1815-1821.
6. J. De Messemaeker et al., "Impact of post-plating anneal and throughsilicon via dimensions on Cu pumping," in Proc. 63rd Electron. Compon. Technol. Conf., Las Vegas, NV, USA, May 2013, pp. 586-591.
7. D. Zhang, K. Hummler, L. Smith, and J. J.-Q. Lu, "Backside TSV protrusion induced by thermal shock and thermal cycling," in Proc. IEEE 63rd Electron. Compon. Technol. Conf., Las Vegas, NV, USA, May 2013, pp. 1407-1413.
8. Y. Li et al., "Impact of Cu TSVs on BEOL metal and dielectric reliability," in Proc. IEEE 63rd Int. Rel. Phys. Symp., Waikoloa, HI, USA, Jun. 2014, pp. 3E.1.1-3E.1.5.
9. J. De Messemaeker et al., "Impact of oxide liner properties on TSV Cu pumping and TSV stress," in Proc. IEEE 63rd Int. Rel. Phys. Symp., Monterey, CA, USA, Apr. 2015, pp. 4C.5.1-4C.5.10.
10. X. Jing et al., "Effect of thermal annealing on TSV Cu protrusion and local stress," in Proc. IEEE 64th Electron. Compon. Technol. Conf., Orlando, FL, USA, May 2014, pp. 1116-1121.
11. N. Nabiollahi et al., "Simulation of Cu pumping during TSV fabrication," in Proc. 14th Euro SimE, Wrocław, Poland, 2013, pp. 1-4.
12. F. X. Che, W. N. Putra, A. Heryanto, A. Trigg, S. Gao, and C. L. Gan, "Numerical and experimental study on Cu protrusion of Cu-filled through-silicon vias (TSV)," in Proc. 64th 3D Syst. Integr. Conf., Osaka, Japan, Jan./Feb. 2012, pp. 1-6.
13. A. D. Trigg et al., "Three dimensional stress mapping of silicon surrounded by copper filled through silicon vias using polychromatorbased multi-wavelength micro Raman spectroscopy," Appl. Phys. Exp., vol. 3, no. 8, pp. 086601-086603, Jul. 2010.
14. C. Okoro, L. E. Levine, R. Xu, K. Hummler, and Y. S. Obeng, "Nondestructive measurement of the residual stresses in copper through-silicon vias using synchrotron-based microbeam X-ray diffraction," IEEE Trans. Electron Devices., vol. 61, no. 7, pp. 2473-2479, Jul. 2014.
15. F. X. Che, W. N. Putra, A. Heryanto, A. Trigg, X. Zhang, and C. L. Gan, "Study on Cu protrusion of through-silicon via," IEEE Trans. Compon., Packag. Manuf. Technol., vol. 3, no. 5, pp. 732-739, May 2013.
16. P. Saettler, M. Boettcher, and K.-J. Wolter, "Characterization of the annealing behavior for copper-filled TSVs," in Proc. IEEE 62nd Electron. Compon. Technol. Conf., San Diego, CA, USA, May/Jun. 2012, pp. 619-624.
17. I. De Wolf et al., "Cu pumping in TSVs: Effect of pre-CMP thermal budget," Microelectron. Rel., vol. 51, nos. 9-11, pp. 1856-1859, 2011.
18. A. Heryanto et al., "Effect of copper TSV annealing on via protrusion for TSV wafer fabrication," J. Electron. Mater., vol. 41, no. 9, pp. 2533-2542, 2012.
19. F. Su, T. Lan, and X. Pan, "Stress evaluation of through-silicon vias using micro-infrared photoelasticity and finite element analysis," Opt. Lasers Eng., vol. 74, pp. 87-93, Nov. 2015.
20. J. W. Dally and W. F. Riley, Experimental Stress Analysis, 3rd ed. New York, NY, USA: McGraw-Hill, Jan. 1991.