Capacitance Expressions and Electrical Characterization of Tapered Through-Silicon Vias for 3-D ICs

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 5, Issue 10, 2015, Pages 1488-1496

  Su, Jinrong ^a   Wang, Fang ^a   Zhang, Wenmei ^a  

^a SHANXI UNIVERSITY   (China)

Author keywords

Insulator capacitance; metal oxide semiconductor (MOS) effect; substrate capacitance; Tapered through silicon vias (T TSVs)

Indexed keywords

ASPECT RATIO; CAPACITANCE; CIRCUIT SIMULATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATED CIRCUITS;

CLOSED-FORM EXPRESSION; ELECTRICAL CHARACTERISTIC; ELECTRICAL CHARACTERIZATION; EQUIVALENT CIRCUIT MODEL; FULL-WAVE SIMULATIONS; INSULATOR CAPACITANCE; SUBSTRATE CAPACITANCE; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84938807874     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2015.2457938     Document Type: Article

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