Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias

IEEE Transactions on Advanced Packaging

Volumn 28, Issue 3, 2005, Pages 356-366

  Schaper, Leonard W ^a   Burkett, Susan L ^a   Spiesshoefer, Silke ^a   Vangara, Gowtham V ^a,b   Rahman, Ziaur ^a   Polamreddy, Swetha ^a  

^a UNIVERSITY OF ARKANSAS   (United States)

^b Hutchinson Technology Incorporated   (United States)

Author keywords

Copper plating; Deep reactive ion etching (DRIE); Reactive ion etching (RIE); Through silicon vias (TSV); Vertically Integrated Sensor Arrays (VISA); Via processing; Z axis interconnects

Indexed keywords

COPPER PLATING; MULTICHIP MODULES; REACTIVE ION ETCHING; SEMICONDUCTING SILICON; VLSI CIRCUITS;

DEEP REACTIVE ION ETCHING (DRIE); THROUGH-SILICON VIAS (TSV); VERTICAL INTEGRATED SENSOR ARRAYS (VISA); Z-AXIS INTERCONNECTS;

ELECTRONICS PACKAGING;

EID: 24644517630     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2005.853271     Document Type: Article

References (21)

1. A. Deutsch, G. V. Kopcsay, C. W. Surovic, B. J. Rubin, L. M. Terman, R. P. Dunne Jr., T. A. Gallo, and R. H. Dennard, "Modeling and characterization of long on chip interconnects for high performance microprocessors," IBM J. Res. Develop., vol. 39, no. 5, pp. 547-566, Sep. 1995.
2. 3)2 and their impact upon large chip performance," IEEE Trans. Compon., Packag., Manuf. Technol. B, vol. 20, no. 4, pp. 361-375, Nov. 1998.
3. P. P. Gelsinger, "Microprocessors for the new millennium: Challenges, opportunities, and new frontiers," in Proc. Int. Solid-State Circuits Conf., 2001, pp. 22-25.
4. W. J. Dally and S. Lacy, "VLSI architecture: Past, present, and future," in Proc. Conf. Adv. Res. VLSI, 1999, pp. 232-241.
5. K. Takahashi, M. Hoshino, H. Yonemura, M. Tomisaka, M. Sunohara, M. Tanioka, T. Sato, K. Kojima, and H. Terao, "Development of advanced 3-D chip stacking technology with ultra-fine interconnection," in Proc. 51st ECTC, 2001, pp. 541-546.
6. Y. Tomita, M. Tago, Y. Nemoto, and K. Takahashi, "Copper bump bonding technologies on 3-D stacked devices," in Dig. 5th VLSI Packaging Workshop Japan, Dec. 2000, pp. 55-57.
7. P. Ramm et al., "InterChip via technology for vertical system integration," in Proc. IEEE Interconnect Technology Conf., 2001, pp. 160-162.
8. L. Schaper and S. Spiesshoefer, "System architecture implications of 3-D interconnect technologies," in Proc. Int. Conf. Advanced Packaging Systems, 2002, pp. 33-37.
9. S. Spiesshoefer and L. Schaper, "IC stacking technology using fine pitch, nanoscale through silicon vias," in Proc. ECTC, 2003, pp. 631-633.
10. F. Läermer, P. Schilp, and R. Bosch Gmbh, "Method of anisotropically etching silicon," U.S. Patent 5501893, 1996; German Patent DE4 241045C1, 1994.
11. A. Ayon, R. Bayt, and K. Breuer, "Deep reactive ion etching: A promising technology for micro- and nanosatellites.," Smart Mater. Structures, pp. 1135-1144, 2001.
12. E. Chow, "Electrical through-wafer interconnects and microfabricated cantilever arrays using through-wafer silicon etching," Ph.D. dissertation, Elec. Eng. Dept., Stanford Univ., Stanford, CA, 2001.
13. K. Chen, A. Ayon, X. Zhang, and S. Spearing, "Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching," J Microelectromach. Syst., vol. 11, no. 3, pp. 264-275, Jun. 2002.
14. J. Yeom, Y. Wu, and M. Shannon, "Critical aspect ratio dependence in deep reactive ion etching of silicon," in Proc. IEEE 12th Int. Conf. Solid State Sensors, Actuators, and Microsystems, 2003, pp. 1631-1634.
15. S. Kenny and K. Matejat, "HDI production using pulse plating with insoluble anodes," CircuiTree, Feb. 21, 2001.
16. "CUBATH SC Data Sheet," Enthone Inc., West Haven, CT, 2001.
17. A. Weinert, P. Amirfeiz, and S. Bengtsson, "Plasma assisted room temperature bonding for MST," Sens. Actuators, A: Phys., vol. 92, no. 1-3, pp. 214-222, Aug. 1, 2001.
18. A. Weinert, P. Amirfeiz, and S. Bengtsson, "Wafer bonding using oxygen plasma treatment in RIE and ICP RIE," in Proc. Joint Meeting - The Electrochemical Society and the Int. Society of Electrochemistry, San Francisco, CA, Sep. 2-7, 2001, p. 1456.
19. M. Sunohara, T. Fujii, M. Hoshino, H. Yonemura, M. Tomisaka, and K. Takahashi, "Development of wafer thinning and double-sided bumping technologies for the three-dimensional stacked LSI," in Proc. 52nd Electronic Components Technology Conf., 2002, pp. 238-245.
20. M. Hendrix, S. Drews, and T. Hurd, "Advantages of wet chemical spin-processing for wafer thinning and packaging applications,," in Proc. 26th IEEE/CPMT Int. Electronics Manufacturing Technology Symp., 2000, pp. 229-236.
21. M. I. Khan, "Deposition of fluorinated silicon nitride using plasma enhanced chemical vapor deposition," M.S. thesis, Elec. Eng, Dept., Univ. Arkansas, Fayetteville, 1990.