Impact of Cu TSVs on BEOL metal and dielectric reliability

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2014, Pages

  Li, Yunlong ^a   Croes, Kristof ^a   Nabiollahi, Nabi ^a,b   Van Huylenbroeck, Stefaan ^a   Gonzalez, Mario ^a   Velenis, Dimitrios ^a   Bender, Hugo ^a   Jourdain, Anne ^a   Pantouvaki, Marianna ^a   Stucchi, Michele ^a   Vanstreels, Kris ^a   Van De Peer, Myriam ^a   De Messemaeker, Joke ^a   Wu, Chen ^a,b   Beyer, Gerald ^a,b   De Wolf, Ingrid ^a   Beyne, Eric ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

BEOL reliability; stress induced voiding (SIV); through silicon vias (TSV); time dependent dielectric breakdown (TDDB)

Indexed keywords

INTEGRATED CIRCUIT INTERCONNECTS; RELIABILITY; THREE DIMENSIONAL INTEGRATED CIRCUITS;

BACK END OF LINES; CU DAMASCENE INTERCONNECTS; DIELECTRIC RELIABILITY; LOW-K MATERIALS; RELIABILITY RISKS; STRESS-INDUCED VOIDING; THROUGH SILICON VIAS; TIME DEPENDENT DIELECTRIC BREAKDOWN;

DIELECTRIC MATERIALS;

EID: 84905647196     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2014.6860630     Document Type: Conference Paper

References (12)

1. E. Beyne, P. De Moor, W. Ruythooren, R. Labie, A. Jourdain, H. Tilmans, and R. Cartuyvels, "Through-silicon via and die stacking technologies for microsystems-integration," IEDM 2008, San Francisco, CA, pp.495-498.
2. A. Mercha, G. Van der Plas, V. Moroz, I. De Wolf, P. Asimakopoulos, N. Minas, and B. Swinnen, "Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance, " IEDM 2010, San Francisco, CA, pp.26-29.
3. W. Guo, G. Van der Plas, A. Ivankovic, V. Cherman, G. Eneman, B. De Wachter, and E. Beyne, "Impact of Through Silicon Via Induced Mechanical Stress on Fully Depleted Bulk FinFET Technology, " IEDM 2012, San Francisco, CA, pp.431-434.
4. J. De Messemaeker, O. Varela Pedreira, B. Vandevelde, H. Philipsen, I. De Wolf, E. Beyne, and K. Croes, "Impact of post-plating anneal and through-silicon via dimensions on Cu pumping, " ECTC 2013, Las Vegas, NV, pp. 586-591.
5. E. T. Ogawa, J. W. McPherson, J. A. Rosal, K. J. Dickerson, T.-C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifield, J. C. Ondrusek, and W. R. McKee, "Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads, " IRPS 2002, Santa Clara, CA, pp. 312-321, 2002
6. B. Li and D. Badami, "Stress Voding Characteristics of Cu/Low k Interconnects Under Long Term Stresses, " IRPS 2012, Anaheim, CA, pp.5E.2.1-5E.2.6
7. H. W. Yao, P. Justison, J. Poppe, "Stress-induced-voiding Risk Factor and Stress Migration Model for Cu Interconnect Reliability," IRPS 2013, Monterey, CA, pp.2C.5.1-2C.5.8
8. G. Bonilla, T.M. Shaw, E.G. Liniger, S. Cohen, S.M. Gates, A. Grill, H. Shobha, C.J. Penny, E. Todd Ryan, "Tailoring Dielectric Materials for Robust BEOL Reliability, " IRPS 2012, Anaheim, CA, pp.3A.1.1-3A.1.6
9. C. Wu, Y. Li, Y. Barbarin, I. Ciofi, B. Tang, T. Kauerauf, K. Croes, J. Bömmels, I. De Wolf, and Z.S. Tkei, "Towards the Understanding of Intrinsic Degradation and Breakdown Mechanisms of a SiOCH Low-k Dielectric, " IRPS 2014, Waikoloa, HI, pp.3A.2.1-3A.2.6
10. A. Redolfi, D. Velenis, S. Thangaraju, P. Nolmans, P. Jaenen, M. Kostermans, . and E. Beyne, "Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers, " ECTC 2011, Lake Buena Vista, FL, pp. 1384-1388.
11. K. Croes, C.J. Wilson, M. Lofrano, Y. Travaly, D. De Roest, Z.S. Tkei, and G.P. Beyer, "Time and Temperature Dependence of Early Stage Stress-Induced-Voiding in Cu/Low-k interconnects," IRPS 2009, Montreal, Canada, pp. 457-463.
12. L. Zhao, Z.S. Tkei, G. Gianni, H. Volders, and G. Beyer, "A new perspective of barrier material evaluation and process optimization," Proc. International Interconnect Technology Conference, June 2009, Sapporo, Japan, pp. 206-208;