Effect of copper TSV annealing on via protrusion for TSV wafer fabrication

Journal of Electronic Materials

Volumn 41, Issue 9, 2012, Pages 2533-2542

  Heryanto, A ^a,b   Putra, W N ^a,c   Trigg, A ^a   Gao, S ^a   Kwon, W S ^a   Che, F X ^a   Ang, X F ^d   Wei, J ^d   I Made, R ^c   Gan, C L ^c   Pey, K L ^b,e  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d SINGAPORE INSTITUTE OF MANUFACTURING TECHNOLOGY   (Singapore)

^e SINGAPORE UNIVERSITY OF TECHNOLOGY AND DESIGN   (Singapore)

Author keywords

3D interconnect; annealing; copper; EBSD; extrusion; nanoindentation; protrusion; TSV

Indexed keywords

3-D PROFILOMETRY; 3D INTERCONNECT; ANNEALING TEMPERATURES; EBSD; ELECTRON BACKSCATTER DIFFRACTION TECHNIQUE; FAILURE MECHANISM; GRAIN ORIENTATION; GRAIN SIZE; HIGH STRESS; HIGH-THROUGHPUT; HIGH-VOLUME MANUFACTURING; INTERCONNECT STRUCTURES; MANUFACTURING YIELD; MICROSTRUCTURAL CHANGES; POTENTIAL THREATS; PROCESS DEVELOPMENT; PROTRUSION; SILICON DEVICES; THERMAL-ANNEALING; THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS; THROUGH SILICON VIAS; TSV; WAFER FABRICATIONS;

ANNEALING; ATOMIC FORCE MICROSCOPY; EXTRUSION; NANOINDENTATION; SCANNING ELECTRON MICROSCOPY; THREE DIMENSIONAL;

COPPER;

EID: 84865209753     PISSN: 03615235     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11664-012-2117-3     Document Type: Article

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