Study on Cu protrusion of through-silicon via

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 3, Issue 5, 2013, Pages 732-739

  Che, F X ^a   Putra, W N ^a,b   Heryanto, A ^a,c   Trigg, Alastair ^a   Zhang, Xiaowu ^a   Gan, C L ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Cu protrusion; finite element analysis (FEA); through silicon via (TSV); wafer annealing

Indexed keywords

3-D INTEGRATED CIRCUIT; ANNEALING TEMPERATURES; ATOMIC FORCE MICROSCOPE (AFM); ELECTRON BACKSCATTER DIFFRACTION TECHNIQUE; FABRICATION PROCESS; GRAIN SIZE DISTRIBUTION; PACKAGING TECHNOLOGIES; THROUGH-SILICON VIA;

ATOMIC FORCE MICROSCOPY; COMPUTER SIMULATION; EXPERIMENTS; FABRICATION; FAILURE (MECHANICAL); FINITE ELEMENT METHOD; GRAIN SIZE AND SHAPE; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS;

ANNEALING;

EID: 84877586259     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2013.2252955     Document Type: Article

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