-
1
-
-
84943578616
-
-
Semiconductor Industry Association, online
-
Intl. Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, 2001 [online] http://public.itrs.net.
-
(2001)
-
-
-
2
-
-
0029756564
-
DDQ Testing for High Performance CMOS - The Next Ten Years
-
DDQ Testing for High Performance CMOS - the Next Ten Years," European Design and Test Conf., Paris, France, Mar. 1996, pp. 578-583.
-
European Design and Test Conf., Paris, France, Mar. 1996
, pp. 578-583
-
-
Williams, T.W.1
-
4
-
-
0030676729
-
DDQ Testing: Issues and Solutions
-
DDQ Testing: Issues and Solutions," European Design and Test Conf., Paris, France, Mar. 1997, pp. 271-278.
-
European Design and Test Conf., Paris, France, Mar. 1997
, pp. 271-278
-
-
Sachdev, M.1
-
5
-
-
0031376341
-
Current Signatures: Application
-
A. Gattiker and W. Maly, "Current Signatures: Application," IEEE Intl. Test Conf., Washington DC, Oct. 1997, pp. 156-165.
-
IEEE Intl. Test Conf., Washington DC, Oct. 1997
, pp. 156-165
-
-
Gattiker, A.1
Maly, W.2
-
6
-
-
0034476294
-
DDQ -based Test Methods
-
DDQ -based Test Methods," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000, pp. 207-216.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000
, pp. 207-216
-
-
Thibeault, C.1
-
7
-
-
0033326421
-
DDQ Testing
-
DDQ Testing," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 1999, pp. 738-746.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 1999
, pp. 738-746
-
-
Maxwell, P.1
-
8
-
-
0033317246
-
DDQ Testing
-
DDQ Testing," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 1999, pp. 730-737.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 1999
, pp. 730-737
-
-
Jandhyala, S.1
-
9
-
-
0034478410
-
DDQ Test Resolution Using Current Prediction
-
DDQ Test Resolution Using Current Prediction," IEEE Intl. Test Conf., Atlantic City, NJ, 2000, pp. 217-224.
-
IEEE Intl. Test Conf., Atlantic City, NJ, 2000
, pp. 217-224
-
-
Variyam, P.N.1
-
10
-
-
0034483640
-
DDQ Data
-
DDQ Data," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000, pp. 189-198.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000
, pp. 189-198
-
-
Daasch, W.R.1
-
11
-
-
0035684387
-
DDQ Limit Setting
-
DDQ Limit Setting," IEEE Intl. Test Conf., Baltimore, MD, Oct. 2001, pp. 82-91.
-
IEEE Intl. Test Conf., Baltimore, MD, Oct. 2001
, pp. 82-91
-
-
Sabade, S.1
Walker, D.M.H.2
-
12
-
-
0034479270
-
DDQ
-
DDQ," IEEE Intl. Test Conf., Atlantic City, NJ, 2000, pp. 199-206.
-
IEEE Intl. Test Conf., Atlantic City, NJ, 2000
, pp. 199-206
-
-
Okuda, Y.1
-
13
-
-
0036444858
-
DDQ Testing with Empirical Linear Prediction
-
DDQ Testing with Empirical Linear Prediction," IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002, pp. 954-963.
-
IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002
, pp. 954-963
-
-
Bergman, D.1
Engler, H.2
-
14
-
-
84862367304
-
DDQ Measurements: A New Test Criterion
-
DDQ Measurements: A New Test Criterion," Design and Automation Test Conf., Los Angeles, CA, June 2000, pp. 645-649.
-
Design and Automation Test Conf., Los Angeles, CA, June 2000
, pp. 645-649
-
-
Diez, J.1
Lopez, J.2
-
15
-
-
0031340072
-
So What is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
-
P. Nigh et al., "So What is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment," IEEE Intl. Test Conf., Washington DC, Oct. 1997, pp. 1037-1038.
-
IEEE Intl. Test Conf., Washington DC, Oct. 1997
, pp. 1037-1038
-
-
Nigh, P.1
-
16
-
-
0035684573
-
DDQ and Other Parametric Data
-
DDQ and Other Parametric Data," IEEE Intl. Test Conf., Baltimore, MD, Oct. 2001, pp. 92-100.
-
IEEE Intl. Test Conf., Baltimore, MD, Oct. 2001
, pp. 92-100
-
-
Daasch, R.1
-
17
-
-
18144365093
-
DDQ Data Analysis
-
DDQ Data Analysis," IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 2002, pp. 381-389.
-
IEEE Intl. Symp. on Defect and Fault Tolerance in VLSI Systems, Vancouver, Canada, Nov. 2002
, pp. 381-389
-
-
Sabade, S.1
Walker, D.M.H.2
-
18
-
-
0002099112
-
DDQ Estimation
-
DDQ Estimation," IEEE Intl. Workshop on Defect Based Testing, Monterey, CA, Apr. 2002, pp. 47-52.
-
IEEE Intl. Workshop on Defect Based Testing, Monterey, CA, Apr. 2002
, pp. 47-52
-
-
Sabade, S.1
Walker, D.M.H.2
-
20
-
-
0034476619
-
Successful Implementation of Structured Testing
-
Ronald Richmond, "Successful Implementation of Structured Testing," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000, pp. 344-348.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000
, pp. 344-348
-
-
Richmond, R.1
-
21
-
-
0030173187
-
On the Effect of Defect Clustering on Test Transparency and IC Test Optimization
-
June
-
A. D. Singh and C. M. Krishna, "On the Effect of Defect Clustering on Test Transparency and IC Test Optimization," IEEE Trans. on Computers, Vol. 45. No. 6, June 1996, pp. 753-757.
-
(1996)
IEEE Trans. on Computers
, vol.45
, Issue.6
, pp. 753-757
-
-
Singh, A.D.1
Krishna, C.M.2
-
22
-
-
51449088512
-
Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies
-
R. Madge et al., "Statistical Post-Processing at Wafersort - An Alternative to Burn-in and a Manufacturable Solution to Test Limit Setting for Sub-micron Technologies," IEEE VLSI Test Symp., Monterey, CA, Apr. 2002, pp. 69-74.
-
IEEE VLSI Test Symp., Monterey, CA, Apr. 2002
, pp. 69-74
-
-
Madge, R.1
-
23
-
-
0034476398
-
DDQ
-
DDQ," IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000, pp. 1051-1059.
-
IEEE Intl. Test Conf., Atlantic City, NJ, Oct. 2000
, pp. 1051-1059
-
-
Keshavarzi, A.1
-
24
-
-
0031341146
-
Screening for Known Good Die Based on Defect Clustering: An Experimental Study
-
A. D. Singh et al., "Screening for Known Good Die Based on Defect Clustering: An Experimental Study," IEEE Intl. Test Conf., Washington DC, 1997, pp. 362-369.
-
IEEE Intl. Test Conf., Washington DC, 1997
, pp. 362-369
-
-
Singh, A.D.1
-
25
-
-
0030686636
-
DDQ and Delay-Fault Testing
-
DDQ and Delay-Fault Testing," IEEE VLSI Test Symp., Monterey, CA, May 1997, pp. 459-464.
-
IEEE VLSI Test Symp., Monterey, CA, May 1997
, pp. 459-464
-
-
Nigh, P.1
-
26
-
-
84943541691
-
The Heisenberg Uncertainty of Test
-
Invited Address
-
P. Maxwell, "The Heisenberg Uncertainty of Test," Invited Address, IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002, p. 13.
-
IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002
, pp. 13
-
-
Maxwell, P.1
-
30
-
-
1542300883
-
Current-Signature-Based Analysis of Complex Test Fails
-
A. Gattiker et al., "Current-Signature-Based Analysis of Complex Test Fails," Intl. Symp. on Test and Failure Analysis, Santa Clara, CA, 1999, pp. 377-387.
-
Intl. Symp. on Test and Failure Analysis, Santa Clara, CA, 1999
, pp. 377-387
-
-
Gattiker, A.1
-
31
-
-
0036444838
-
DD Outliers Using Feed-Forward Voltage Testing
-
DD Outliers Using Feed-Forward Voltage Testing," IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002, pp. 673-682.
-
IEEE Intl. Test Conf., Baltimore, MD, Oct. 2002
, pp. 673-682
-
-
Madge, R.1
-
32
-
-
0035680818
-
Unit Level Predicted Yield: A Method of Identifying High Defect Density Die at Wafer Sort
-
R. B. Miller and W. C. Riordan, "Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort," IEEE Intl. Test Conf., Baltimore, MD, 2001, pp. 1118-1127.
-
IEEE Intl. Test Conf., Baltimore, MD, 2001
, pp. 1118-1127
-
-
Miller, R.B.1
Riordan, W.C.2
|