Improved wafer-level spatial analysis for IDDQ limit setting

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 82-91

  Sabade, Sagar ^a   Walker, D M H ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEFECTS; ELECTRIC CURRENTS; PROBABILITY; VECTORS; WSI CIRCUITS;

WAFER-LEVEL SPATIAL ANALYSIS;

CHIP SCALE PACKAGES;

EID: 0035684387     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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