Variance reduction using wafer patterns in IddQ data

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 189-198

  Daasch, W Robert ^a   McNames, James ^a   Bockelman, Daniel ^a   Cota, Kevin ^a   Madge, Robert ^a  

^a PORTLAND STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; ELECTRIC CURRENT DISTRIBUTION; ELECTRIC FAULT CURRENTS; SEMICONDUCTOR DEVICE TESTING;

SETTING THRESHOLD LIMITS; SINGLE THRESHOLD TEST; VARIANCE REDUCTION; WAFER PATTERNS;

CMOS INTEGRATED CIRCUITS;

EID: 0034483640     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)