Unit Level Predicted Yield: A method of identifying high defect density die at wafer sort

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1118-1127

  Miller, Russell B ^a   Riordan, Walter C ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CRYSTAL DEFECTS; ELECTRONICS PACKAGING; FAILURE ANALYSIS;

SEMICONDUCTOR WAFERS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0035680818     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. A defect model of reliability
2. Relation between yield and reliability of integrated circuits: Experimental results and application to continuous early failure rate reduction programs
3. Microprocessor reliability performance as a function of die location for a 0.25μ, five layer metal CMOS logic process
4. A PROM element based on salicide agglomeration of poly fuses in a CMOS logic process