On the effect of defect clustering on test transparency and IC test optimization

IEEE Transactions on Computers

Volumn 45, Issue 6, 1996, Pages 753-757

  Singh, A D ^a   Krishna, C M ^b  

^a AUBURN UNIVERSITY   (United States)

^b University of Massachusetts   (United States)

Author keywords

Adaptive testing; Defect clustering; IC test optimization; Wafer based testing

Indexed keywords

DEFECTS; ELECTRIC FAULT CURRENTS; ELECTRIC FAULT LOCATION; FUNCTIONS; MATHEMATICAL MODELS; OPTIMIZATION;

ADAPTIVE TESTING; DEFECT CLUSTERING; NEGATIVE BINOMIAL FUNCTION; TEST OPTIMIZATION; TEST TRANSPARENCY;

INTEGRATED CIRCUIT TESTING;

EID: 0030173187     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.506431     Document Type: Article

References (13)

1. W. H. Beyer, Handbook of Mathematical Sciences. Boca Raton, Fla.: CRC Press, 1987.
2. D.V. Das, S.C. Seth, P.T. Wagner, J.C. Anderson, and V.D. Agrawal, "An Experimental Study on Reject Ratio Prediction for VLSI Circuits: Kokomo Revisited," Proc. Int'l Test Conf., pp. 712-720, 1990.
3. M.H. DeGroot, Optimal Statistical Decisions. New York: McGraw-Hill, 1970.
4. R.B. Elo, "An Empirical Relationship Between Test Transparency and Fault Coverage," Proc. Int'l Test Conf., pp. 1,006-1,011, 1990.
5. I. Koren and D.K. Pradhan, "Introducing Redundancy into VLSI Designs for Yield and Performance Enhancement," Proc. FTCS-15, pp. 330-335, 1985.
6. D.L. Luenberger, Introduction to Linear and Nonlinear Programming. Reading, Mass.: Addison-Wesley, 1973.
7. E.J. McCluskey, "IC Quality and Test Transparency," Proc. Int'l Test Conf., pp. 295-301, 1988.
8. S.C. Seth and V.D. Agrawal, "On the Probability of Fault Occurrence," Defect and Fault-Tolerance in VLSI Systems, pp. 47-52. New York: Plenum, 1989.
9. S.C. Seth and V.D. Agrawal, "Characterizing the LSI Yield Equation from Wafer Test Data," IEEE Trans. Computer-Aided Design, vol. 3, 1984.
10. A.D. Singh and C.M. Krishna, "Chip Test Optimization Using Defect Clustering Information," Proc. 22nd IEEE Int'l Symp. Fault Tolerant Computing, pp. 366-373, 1992.
11. A.D. Singh and C.M. Krishna, "On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction," IEEE Trans. Computer-Aided Design, vol. 13, no. 5, pp. 295-301, 1993.
12. C.H. Stapper, "Correlation Analysis of Particle Clusters on Integrated Circuit Wafers," IBM J. Research and Development, vol. 31, no. 6, 1987.
13. T.W. Williams and N.C. Brown, "Defect Level as a Function of Fault Coverage," IEEE Trans. Computers, vol. 30, no. 12, pp. 987-988, Dec. 1981.