Fast and accurate protocol specific bus modeling using TLM 2.0

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 316-319

  Van Moll, H W M ^a   Corporaal, H ^a   Reyes, V ^b   Boonen, M ^b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; LARGE SCALE SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

ABSTRACTION LEVEL; BUS-BASED COMMUNICATION; CYCLE ACCURATE; DESIGN CYCLE; SIMULATION SPEED; SYSTEMS ON CHIPS; TRANSACTION LEVEL MODELING; TRANSACTION LEVEL MODELS;

INTEGRATED CIRCUIT DESIGN;

EID: 70350047088     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090680     Document Type: Conference Paper

References (11)

1. TLM 2 Whitepaper. May 2007. www.systemc.org [2] L. Cai and D. Gajski, "Transaction Level Modeling: An Overview", CODES+ISSS. Oct. 2003.
2. S. Pasricha, N. Dutt, M. Ben-Romdhane. "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", DAC'04, June 2004.
3. IBM. CoreConnect SystemC TLMs. www.ibm.com
4. Open Core Protocol International Partnership (OCP-IP). A SystemC OCP Transaction Level Communication Channel. www.ocpip.org
5. ARM RealView ESL APIs. www.arm.com
6. Open SystemC Initiative (OSCI) TLM2 User Manual
7. SystemC Modeling Library (SCML). CoWare. www.coware.com
8. ARM Ltd. AMBA Protocol Specification. www.arm.com
9. Specman verification environment www.cadence.com
10. P. Klapproth, "Architectural Concept for IP re-use", in VLSI ASP DAC, December 2002
11. H.W.M. van Moll, "Cycle-Accurate and Protocol Specific Modeling Methodology Using TLM 2.0" http://xt82.myftp.org/thesis